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| april 2004 1/294 this is preliminary information on a new product now in development. details are subject to change without notice. rev. 2.1 ST7MC1/st7mc2 8-bit mcu with nested interrupts, flash, 10-bit adc, brushless motor control, five timers, spi, linsci ? product preview memories ? 8k to 60k dual voltage flash program mem- ory or rom with read-out protection capabili- ty. in-application programming and in-circuit programming. ? 384 to 1.5k ram ? hdflash endurance: 100 cycles, data reten- tion: 20 years clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and auxiliary voltage detector (avd) with interrupt capability ? clock sources: crystal/ceramic resonator os- cillators and by-pass for external clock, clock security system. ? four power saving modes: halt, active-halt, wait and slow interrupt management ? nested interrupt controller ? 14 interrupt vectors plus trap and reset ? mces top level interrupt pin ? 16 external interrupt lines (on 3 vectors) up to 60 i/o ports ? up to 60 multifunctional bidirectional i/o lines ? up to 41 alternate function lines ? up to 11 high sink outputs 5 timers ? main clock controller with: real time base, beep and clock-out capabilities ? configurable window watchdog timer ? two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input, pwm and pulse generator modes ? 8-bit pwm auto-reload timer with: 2 input captures, 4 pwm outputs, output compare and time base interrupt, external clock with event detector 2 communication interfaces ? spi synchronous serial interface ? lin sci ? asynchronous serial interface brushless motor control peripheral ? 6 high sink pwm output channels for sine- wave or trapezoidal inverter control ? motor safety including asynchronous emer- gency stop and write-once registers ? 4 analog inputs for rotor position detection (sensorless/hall/tacho/encoder) ? permanent magnet motor coprocessor includ- ing multiplier, programmable filters, blanking windows and event counters ? operational amplifier and comparator for cur- rent/voltage mode regulation and limitation analog peripheral ? 10-bit adc with 16 input pins in-circuit debug instruction set ? 8-bit data manipulation ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction ? true bit manipulation development tools ? full hardware/software development package device summary tqfp64 14 x 14 tqfp80 14 x 14 tqfp32 7 x 7 sdip56 tqfp44 10 x 10 sdip32 features ST7MC1 st7mc2 program memory - bytes 8k 16k 24k 32k 48k 60k ram (stack) - bytes 384 (256) 768 (256) 1024 (256) 1024 (256) 1536 (256) 1536 (256) peripherals watchdog, 16-bit timer a, linsci ? , 10-bit adc, mtc, 8-bit pwm art, icd - spi, 16-bit timer b operating supply vs. frequency 4.5 to 5.5v with f cpu 8mhz temperature range -40c to +85c / -40c to +125c -40c to +85 c package sdip32/tqfp32 tqfp44 sdip56/tqfp64 tqfp64 tqfp80 1
table of contents 294 2/294 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 main clock controller with real time clock and beeper (mcc/rtc) . 32 6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 6.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.7 external interrupt control register (eicr) . . . . . . . . . . . . . . . . . . . . . . . 43 7 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 7.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 pwm auto-reload timer (art) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.5 linsci serial communication interface (lin master/slave) . . . . . . . . . 103 table of contents 3/294 9.6 motor controller (mtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.7 operational amplifier (oa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 9.8 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 10 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.1 cpu addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 11 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 11.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 11.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 11.3 6operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 11.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 11.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 11.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11.11 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 266 11.12 motor control characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 11.13 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.14 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 12 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 12.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 13 st7mc device configuration and ordering information . . . . . . . . . . . . . . . . 284 13.1 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.2 device ordering information and transfer of customer code . . . . 286 13.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 ST7MC1/st7mc2 4/294 1 introduction the st7mcx device is member of the st7 micro- controller family designed for mid-range applica- tions with a motor control dedicated peripheral. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set and are available with flash, rom or fastrom program memory. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or stand-by state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (8k - 60k bytes) v dd reset port d pd7:0 (8-bits) timer a 10-bit adc port a ram (384 - 1536bytes) port b mcc/rtc/beep 1 v aref v ssa port e 1 timer b 1 pe5:0 (6-bits) mtc volt input pa7:0 1) (8-bits) port f 1 pf5:0 (6-bits) spi 1 pb7:0 (8-bits) v ss watchdog osc lvd osc2 memory sci/lin avd pwm art port c (8-bits) motor control pc7:0 port g 1) port h 1) pg7:0 1) (8-bits) ph7:0 1) (8-bits) mces on some devices only, see table 1, ? st7mc device pin description, ? on page 11 debug module 1 ST7MC1/st7mc2 5/294 2 pin description figure 2. 80-pin tqfp 14x14 package pinout 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pd3 / icap1_a / ain13 pd2 / icap2_a / ain12 pd1 (hs) / ocmp1_a pf0 / mcdem / ain8 v dd_0 vss_0 vssa pd0 / ocmp2_a / ain11 ph3 ph2 ph1 pf4 (hs) pf1 / mczem / ain9 pg1 pg2 pg3 osc1 ain2 / pa7 vdd_1 pg0 osc2 pwm3 / pa0 pwm2 / (hs) pa1 pwm1 / pa2 ain0 / pwm0 / pa3 artclk / (hs) pa4 ain1 / artic1 / pa5 artic2 / pa6 (hs) mco3 (hs) mco4 (hs) mco5 pg4 pg5 (hs) pc0 ain5 / mccfi 0/ pc1 mcpwmu/ pc5 miso / pb4 ain3 / mosi / pb5 sck / (hs) pb6 ain4 /ss /(hs) pb7 oap / pc2 oan / pc3 ain6 / mccfi 1/ oaz 40 mcpwmv/ pc6 21 22 24 23 mcvref / pb0 mcia / pb1 mcib / pb2 mcic / pb3 vpp/iccsel pe5 pe4 / extclk_b mco2 (hs) mco1 (hs) mco0 (hs) reset pf3 (hs) / beep pf5 (hs) ph0 pg6 pg7 varef pc7 / mcpwmw / ain7 * mccref / pc4 pe3 / icap1_b ph7 ph6 ph5 pe2 / icap2_b pe1 / ocmp1_b pe0 (hs) / ocmp2_b ph4 pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata vdd_2 vss_2 pd4 /extclk_a / ain14 / iccclk pf2 / mco / ain10 vss_1 ei0 ei2 ei2 ei1 ei1 (hs) 20ma high sink capability eix associated external interrupt vector mces * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 6/294 figure 3. 64-pin tqfp 14x14 package pinout miso / pb4 ain3 / mosi / pb5 sck / (hs) pb6 ain4 / ss /(hs) pb7 (hs) pc0 ain5 / mccfi0 / pc1 oap / pc2 oan / pc3 ain6 / mccfi1 / oaz * mccref / pc4 mcpwmu / pc5 mcpwmv/ pc6 mcvref / pb0 mcia / pb1 mcib / pb2 mcic / pb3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei0 ei1 v ss _1 v dd _1 osc1 osc2 pwm3 / pa0 pwm2 / (hs) pa1 pwm1 / pa2 ain0 / pwm0 / pa3 artclk / (hs) pa4 ain1 / artic1 / pa5 artic2 / pa6 ain2 / pa7 (hs) mco3 (hs) mco4 (hs) mco5 mces pf5 (hs) pf4 (hs) pf3 (hs) / beep pf2 / mco / ain10 pf1 / mczem / ain9 pf0 / mcdem / ain8 reset v dd_0 v aref v ssa v ss_0 pc7 / mcpwmw / ain7 pd3 / icap1_a / ain13 pd2 / icap2_a / ain12 pd1 (hs) / ocmp1_a pd0 / ocmp2_a / ain11 pe5 / pe4 / extclk_b pe3 / icap1_b pe2 / icap2_b pe1 / ocmp1_b pe0 (hs) / ocmp2_b v dd _2 v ss _2 pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata pd4 /extclk_a / ain14 / iccclk mco2 (hs) mco1 (hs) mco0 (hs) v pp / iccsel (hs) 20ma high sink capability eix associated external interrupt vector ei1 * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 7/294 figure 4. 32-pin sdip package pinouts iccsel / v pp mco0 mco1 mco2 mco3 mco4 mco5 mces osc1 osc2 ain0 / pwm0 / pa3 ain1 / artic1 / pa5 mcvref / pb0 mcia / pb1 mcib / pb2 mcic / pb3 pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata pd4 / extclk_a / ain14 / iccclk pd3 / icap1_a / ain13 pd2 / icap2_a / mczem / ain12 pd1 (hs) / ocmp1_a / mcpwmv / mcdem pd0 / ocmp2_a / mcpwmw / ain11 reset v dd_0 v ss_0 v aref pc4 / mccref * oaz / mccfi1 / ain6 pc3 / oan pc2 / oap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ei1 ei2 ei0 (hs) 20ma high sink capability eix associated external interrupt vector * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 8/294 figure 5. 56-pin sdip package pinouts 52 51 50 49 48 47 46 45 44 43 42 41 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 53 54 55 56 (hs) mco1 (hs) mco0 v pp /iccsel icap1_b / pe3 icap2_b / pe2 ocmp1_b / pe1 21 20 17 18 19 mces (hs) mco5 (hs) mco4 (hs) mco3 (hs) mco2 40 39 38 37 36 23 22 28 27 24 25 26 35 34 33 32 31 30 29 osc2 osc1 vdd_1 vss_1 pwm2 / (hs) pa1 ain0 / pwm0 / pa3 artclk / (hs) pa4 ain1 / artic1 / pa5 artic2 / pa6 miso / pb4 ain3 / mosi / pb5 sck / (hs) pb6 ain4 / ss /(hs) pb7 mcvref / pb0 mcia / pb1 mcib / pb2 mcic / pb3 pf3 (hs) / beep pf1 / mczem / ain9 pf0 / mcdem / ain8 reset v dd_0 v aref v ssa v ss_0 pc7 / mcpwmw / ain7 pd3 / icap1_a / ain13 pd2 / icap2_a / ain12 pd1 (hs) / ocmp1_a pd0 / ocmp2_a / ain11 pe0 (hs) / ocmp2_b v dd _2 v ss _2 pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata pd4 /extclk_a / ain14 / iccclk oaz / mccfi1 / ain6 pc4 / mccref * pc3 / oan pc2 / oap pc6 / mcpwmv pc5 / mcpwmu pc1 / mccfi0/ain5 pc0(hs) ei0 ei2 ei1 ei1 ei2 (hs) 20ma high sink capability eix associated external interrupt vector * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 9/294 figure 6. 44-pin tqfp package pinouts miso / pb4 ain3 / mosi / pb5 sck / (hs) pb6 ain4 / ss /(hs) pb7 oap / pc2 oan / pc3 ain6 / mccfi1 / oaz * mccref / pc4 mcia / pb1 mcib / pb2 mcic / pb3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei0 ei1 v ss _1 osc1 osc2 ain0 / pwm0 / pa3 ain1 / artic1 / pa5 mcvref / pb0 (hs) mco3 (hs) mco4 (hs) mco5 mces pd0 / ocmp2_a / ain11 reset v dd_0 v aref v ssa v ss_0 pc7 / mcpwmw / ain7 pd4 /extclk_a / ain14 / iccclk pd3 / icap1_a / ain13 pd2 / icap2_a / mczem / ain12 pd1 (hs) / ocmp1_a / mcpwmv/mcdem pe3 / icap1_b pe2 / icap2_b pe1 / ocmp1_b pe0 (hs) / ocmp2_b pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata mco2 (hs) mco1 (hs) mco0 (hs) v pp / iccsel eix associated external interrupt vector (hs) 20ma high sink capability v dd _1 * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 10/294 figure 7. 32-pin tqfp 7x7 package pinout mcic / pb3 oap / pc2 oan / pc3 ain6 / mccfi1 / oaz * mccref / pc4 mcvref / pb0 mcia / pb1 mcib / pb2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 ei1 ei0 osc1 osc2 ain0 / pwm0 / pa3 ain1 / artic1 / pa5 (hs) mco3 (hs) mco4 (hs) mco5 mces reset v dd_0 v aref v ss_0 pd3 / icap1_a / ain13 pd2 / icap2_a / mczem / ain12 pd1 (hs) / ocmp1_a / mcpwmv / mcdem pd0 / ocmp2_a / mcpwmw /ain11 pd7 (hs) / tdo pd6 (hs) / rdi pd5 / ain15 / iccdata pd4 /extclk_a / ain14 / iccclk mco2 (hs) mco1 (hs) mco0 (hs) v pp /iccsel ei2 eix associated external interrupt vector (hs) 20ma high sink capability * once the mtc peripheral is on, the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o 1 ST7MC1/st7mc2 11/294 pin description (cont ? d) for external pin connection guidelines, see ? electrical characteristics ? on page 243. legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c t = cmos 0.3v dd /0.7v dd with schmitt trigger t t = refer to the g&h ports characteristics in section 11.8.1 on page 260 output level: hs = 20ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt 1) , ana = analog ? output: od = open drain, pp = push-pull refer to ? i/o ports ? on page 50 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 1. st7mc device pin description pin n pin name type level port main function (after reset) alternate function 2) tqfp80 tqfp64 sdip56 tqfp44 sdip32 tqfp32 input output input outp ut float wpu int ana od pp 118151mco3 (hs) o hs xmotor control output 3 229262mco4 (hs) o hs xmotor control output 4 3 3 10 3 7 3 mco5 (hs) o hs x motor control output 5 4411484mces 3) ic t input wpd + int mtc emergency stop 5-----pg0 i/ot t x xxxport g0 6-----pg1 i/ot t x xxxport g1 7-----pg2 i/ot t x xxxport g2 8-----pg3 i/ot t x xxxport g3 9512595osc1 4) i external clock input or resonator os- cillator inverter input 106136106osc2 4) i/o resonator oscillator inverter output 11 7 14 7 - - v ss_1 s digital ground voltage 12 8 15 8 - - v dd_1 s digital main supply voltage 139----pa0/pwm3 i/oc t x x x x port a0 pwm output 3 14 10 16 - - - pa1/pwm2 i/o c t hs x x x x port a1 pwm output 2 1511----pa2pwm1 i/oc t x x x x port a2 pwm output 1 16 12 17 9 11 7 pa3/pwm0/ ain0 i/o c t x ei1 x x x port a3 pwm out- put 0 adc ana- log input 0 17 13 18 - - - pa4 (hs)/art- clk i/o c t hs x x x x port a4 pwm-art external clock 18 14 19 10 12 8 pa5 / artic1/ ain1 i/o c t x ei1 x x x port a5 pwm-art input cap- ture 1 adc analog input 1 19 15 20 - - - pa6 / artic2 i/o c t x ei1 x x port a6 pwm-art input capture 2 2016----pa7/ain2 i/oc t x ei1 x x x port a7 adc analog input 2 1 ST7MC1/st7mc2 12/294 21 17 21 11 13 9 pb0/mcvref i/o c t x x x x x port b0 mtc voltage reference 22 18 22 12 14 10 pb1/mcia i/o c t x x x x x port b1 mtc input a 23 19 23 13 15 11 pb2/mcib i/o c t x x x x x port b2 mtc input b 24 20 24 14 16 12 pb3/mcic i/o c t x x x x x port b3 mtc input c 25 21 25 15 - - pb4/miso i/o c t x xxxport b4 spi master in / slave out data 26 22 26 16 - - pb5/mosi/ ain3 i/o c t x xxxport b5 spi master out / slave in data adc ana- log input 3 27 23 27 17 - - pb6/sck i/o c t hs x ei2 x x port b6 spi serial clock 28 24 28 18 - - pb7/ss /ain4 i/o c t hs x ei2 x x port b7 spi slave select (ac- tive low) adc ana- log input 4 29-----pg4 i/ot t x xxxport g4 30-----pg5 i/ot t x xxxport g5 31-----pg6 i/ot t x xxxport g6 32-----pg7 i/ot t x xxxport g7 33 25 29 - - - pc0 i/o c t hs x ei2 x x port c0 34 26 30 - - - pc1/mccfi0 5) /ain5 i/o c t x ei2 xxxport c1 mtc cur- rent feed- back input 0 5) adc ana- log input 5 35 27 31 19 17 13 pc2/oap i/o c t x ei2 x x x port c2 opamp positive input 36 28 32 20 18 14 pc3/oan i/o c t x ei2 x x x port c3 opamp negative input 37 29 33 21 19 15 oaz/ mccfi1 5) / ain6 i/o x opamp output mtc cur- rent feed- back input 1 5) adc analog input 6 38 30 34 22 20 16 pc4/mccref i/o c t x x xxxport c4 mtc current feedback reference 9) 39 31 35 - - - pc5/mcpw- mu i/o c t x x x x port c5 mtc pwm output u 40 32 36 - - - pc6/ mcpwmv 7) i/o c t x x x x port c6 mtc pwm output v 7) 41 33 37 23 - - pc7/ mcpwmw 7) / ain7 i/o c t x x xxxport c7 mtc pwm output w 7) adc analog input 7 42 34 38 24 21 17 v aref i analog reference voltage for adc 43 35 39 25 - - v ssa s analog ground voltage 44 36 40 26 22 18 v ss_0 s digital ground voltage 45 37 41 27 23 19 v dd_0 s digital main supply voltage 46 38 42 28 24 20 reset i/o c t top priority non maskable interrupt pin n pin name type level port main function (after reset) alternate function 2) tqfp80 tqfp64 sdip56 tqfp44 sdip32 tqfp32 input output input outp ut float wpu int ana od pp 1 ST7MC1/st7mc2 13/294 47 39 43 - - - pf0/ mcdem 6) / ain8 i/o c t x x x x x port f0 mtc de- magnetiza- tion output 6) adc ana- log input 8 48 40 44 - - - pf1/mczem 6) / ain9 i/o c t x x x x x port f1 mtc bemf output 6) adc ana- log input 9 4941---- pf2/mco/ ain10 i/o c t x x x x x port f2 main clock out (f osc /2) adc ana- log input 10 50 42 45 - - - pf3/beep i/o c t hs x x x x port f3 beep signal output 5143----pf4 i/oc t hs x xxxport f4 5244----pf5 i/oc t hs x xxxport f5 53-----ph0 i/ot t x xxxport h0 54-----ph1 i/ot t x xxxport h1 55-----ph2 i/ot t x xxxport h2 56-----ph3 i/ot t x xxxport h3 57 45 46 29 25 21 pd0/ ocmp2_a/ mcpwmw 7) / ain11 i/o c t x xxxport d0 timer a output compare 2 mtc pwm output w 7) adc analog input 11 58 46 47 30 26 22 pd1 (hs)/ ocmp1_a/ mcpwmv 7) / mcdem 6) i/o c t hs x ei0 x x port d1 timer a output compare 1 mtc pwm output v 7) mtc demagnetization 6) 59 47 48 31 27 23 pd2/icap2_a/ mczem5) / ain12 i/o c t x ei0 xxxport d2 timer a input capture 2 mtc bemf 6) adc analog input 12 60 48 49 32 28 24 pd3/icap1_a/ ain13 i/o c t x ei0xxxport d3 timer a in- put capture 1 adc analog input 13 61 49 50 33 29 25 pd4/ extclk_a/ic- cclk/ain14 i/o c t x ei0 xxxport d4 timer a external clock source icc clock output adc analog input 14 62 50 51 34 30 26 pd5/iccda- ta/ain15 i/o c t x ei0 xxxport d5 icc data input adc analog input 15 63 51 52 35 31 27 pd6/rdi i/o c t hs x ei0 x x port d6 sci receive data in 64 52 53 36 32 28 pd7/tdo i/o c t hs x x x x port d7 sci transmit data output 65 53 54 - - - v ss_2 s digital ground voltage 66 54 55 - - - v dd_2 s digital main supply voltage 67-----ph4 i/ot t x xxxport h0 68-----ph5 i/ot t x xxxport h10 69-----ph6 i/ot t x xxxport h2 70-----ph7 i/ot t x xxxport h3 pin n pin name type level port main function (after reset) alternate function 2) tqfp80 tqfp64 sdip56 tqfp44 sdip32 tqfp32 input output input outp ut float wpu int ana od pp 1 ST7MC1/st7mc2 14/294 notes : 1. in the interrupt input column, ? eix ? defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. if two alternate function outputs are enabled at the same time on a given pin (for instance, mcpwmv and mcdem on pd1 on tqfp32), the two signals will be ored on the output pin. 4. osc1 and osc2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla- tor; see section 1 introduction and section 11.5 clock and timing characteristics for more details. 5. mccfi can be mapped on 2 different pins on 80 ,64 and 56-pin packages. this allows: - either to use pc1 as a standard i/o and map mccfi on aoz with or without using the operational am- plifier (selected case after reset), - or to map mccfi on pc1 and use the amplifier for another function. the mapping can be selected in mref register of motor control cell. see section motor control for more details. 6. mczem is mapped on pf1 on 80, 64 and 56-pin packages and on pd2 on 44 and 32-pins. mcdem is mapped on pf0 on 80, 64 and 56-pin packages and on pd1 on 44 and 32-pin packages. 7. mcpwmv is mapped on pc6 on 80 and 64-pin packages and on pd1 on 44,and 32-pins packages. mcpwmw is mapped on pc7 on 80, 64 and 44-pin packages and on pd0 on 32-pins package. 8. on the chip, each i/o port has 8 pads. pads that are not bonded to external pins are in input pull-up configuration after reset. the configuration of these pads must be kept at reset state to avoid added cur- rent consumption. 9. once the mtc peripheral is on (bits cke=1 or dac=1 in the register mcra), the pin pc4 is configured to an alternate function. pc4 is no longer usable as a digital i/o. 71 55 56 37 - - pe0/ ocmp2_b i/o c t hs x x x x port e0 timer b output compare 2 7256138- - pe1/ ocmp1_b i/o c t x x x x x port e1 timer b output compare 1 73 57 2 39 - - pe2/icap2_b i/o c t x x x x port e2 timer b input capture 2 74 58 3 40 - - pe3/icap1_b/ i/o c t x x x x x port e3 timer b input capture 1 7559---- pe4/ extclk_b i/o c t x xxxport e4 timer b external clock source 7660----pe5 i/oc t x x x x x port e5 77 61 4 41 1 29 v pp /iccsel i must be tied low. in the programming mode when available, this pin acts as the programming voltage input v pp ./ icc mode pin. see section 11.9.2 on page 264 78 62 5 42 2 30 mco0 (hs) o hs x mtc output channel 0 79 63 6 43 3 31 mco1 (hs) o hs x mtc output channel 1 80 64 7 44 4 32 mco2 (hs) o hs x mtc output channel 2 pin n pin name type level port main function (after reset) alternate function 2) tqfp80 tqfp64 sdip56 tqfp44 sdip32 tqfp32 input output input outp ut float wpu int ana od pp 1 ST7MC1/st7mc2 15/294 3 register & memory map as shown in figure 8 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 2kbytes of ram and up to 60kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. important: memory locations marked as ? re- served ? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. figure 8. memory map as shown in figure 9 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, up to 1536 bytes of ram and up to 60 kbytes of user program memo- ry. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. 0000h ram program memory (60k, 48k, 32k, 24k, 8k) interrupt & reset vectors hw registers 0080h 007fh 0fffh (see table 2 ) 1000h ffdfh ffe0h ffffh (see table 8 ) 0680h reserved 067fh short addressing ram (zero page) 256 bytes stack 16-bit addressing ram 0100h 01ffh 01ffh 0080h 0200h 00ffh 1000h 32 kbytes 60 kbytes ffffh 8000h (1536/1024 or 047fh 8 kbytes e000h 768/384 bytes) or 037fh or 067fh 24 kbytes a000h 48 kbytes 4000h 1 ST7MC1/st7mc2 16/294 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 2) 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 0006h 0007h 0008h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0009h 000ah 000bh port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w 2) r/w 2) 000fh 0010h 0011h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0012h 0013h 0014h port g pgdr pgddr pgor port g data register port g data direction register port g option register 00h 1) 00h 00h r/w r/w r/w 0015h 0016h 0017h port h phdr phddr phor port h data register port h data direction register port h option register 00h 1) 00h 00h r/w r/w r/w 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh lin sci ? scisr scidr scibrr scicr1 scicr2 scicr3 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci control register 3 sci extended receive prescaler register sci extended transmit prescaler register c0h xxh 00h xxh 00h 00h 00h 00h read only r/w r/w r/w r/w r/w r/w r/w 0020h reserved area (1 byte) 0021h 0022h 0023h spi spidr spicr spicsr spi data i/o register spi control register spi control/status register xxh 0xh 00h r/w r/w r/w 0024h 0025h 0026h 0027h 0028h itc itspr0 itspr1 itspr2 itspr3 eicr interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 external interrupt control register ffh ffh ffh ffh 00h r/w r/w r/w r/w r/w 1 ST7MC1/st7mc2 17/294 0029h flash fscr flash control/status register 00h r/w 002ah 002bh watchdog wwdgcr window watchdog control register 7fh r/w wwdgwr window watchdog window register 7fh r/w 002ch 002dh mcc mccsr mccbcr main clock control / status register main clock controller: beep control register 00h 00h r/w r/w 002eh 002fh 0030h adc adccsr adcdrmsb adcdrlsb control/status register data register msb data register lsb 00h 00h 00h r/w read only read only 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tacsr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a control/status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h sim sicsr system integrity control/status register 000x000x b r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbcsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b control/status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only read only read only read only read only read only r/w r/w address block register label register name reset status remarks 1 ST7MC1/st7mc2 18/294 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah mtc (page 0) mtim mtiml mzprv mzreg mcomp mdreg mwght mprsr mimr misr mcra mcrb mcrc mphst mdfr mcfr mref mpcr mrep mcpwh mcpwl mcpvh mcpvl mcpuh mcpul mcp0h mcp0l timer counter high register timer counter low register capture z n-1 register capture z n register compare c n+1 register demagnetization register a n weight register prescaler & sampling register interrupt mask register interrupt status register control register a control register b control register c phase state register d event filter register current feedback filter register reference register pwm control register repetition counter register compare phase w preload register high compare phase w preload register low compare phase v preload register high compare phase v preload register low compare phase u preload register high compare phase u preload register low compare phase 0 preload register high compare phase 0 preload register low 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0fh ffh r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h mtc (page 1) mdtg mpol mpwme mconf mpar mzrf mscr dead time generator enable polarity register pwm register configuration register parity register z event filter register sampling clock register ffh 3fh 00h 02h 00h 0fh 00h see mtc description 0057h to 006ah reserved area (4 bytes) 006bh 006ch 006dh 006eh 006fh 0070h dm dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l debug control register debug status register debug breakpoint 1 msb register debug breakpoint 1 lsb register debug breakpoint 2 msb register debug breakpoint 2 lsb register 00h 10h ffh ffh ffh ffh r/w read only r/w r/w r/w r/w address block register label register name reset status remarks 1 ST7MC1/st7mc2 19/294 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr articcsr articr1 articr2 pwm ar timer duty cycle register 3 pwm ar timer duty cycle register 2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register ar timer input capture control/status reg. ar timer input capture register 1 ar timer input capture register 2 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only 007fh opamp oacsr opamp control/status register 00h r/w address block register label register name reset status remarks 1 ST7MC1/st7mc2 20/294 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a byte-by-byte ba- sis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features three flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be pro- grammed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be pro- grammed or erased without removing the de- vice from the application board. ? iap (in-application programming) in this mode, all sectors except sector 0, can be pro- grammed or erased without removing the de- vice from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection against piracy register access security system (rass) to prevent accidental programming or erasing 4.3 structure the flash memory is organised in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see table 3 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flash memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 9 ). they are mapped in the upper part of the st7 addressing space so the reset and in- terrupt vectors are located in sector 0 (f000h- ffffh). table 3. sectors available in flash devices 4.3.1 read-out protection read-out protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. in flash devices, this protection is removed by re- programming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. figure 9. memory map and sector address flash size (bytes) available sectors 4k sector 0 8k sectors 0,1 > 8k sectors 0,1, 2 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k 1 ST7MC1/st7mc2 21/294 flash program memory (cont ? d) 4.4 icc interface icc needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see figure 10 ). these pins are: ? reset : device reset ? v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input/output serial data pin ? iccsel/v pp : programming voltage ? osc1(or oscin): main clock input for exter- nal source (optional) ? v dd : application board power supply (option- al, see figure 10 , note 3) figure 10. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icc session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. w hen using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or os- cin pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. st7 devices with multi-oscillator capability need to have osc2 grounded in this case. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 975 3 programming tool icc connector application board icc cable (see note 3) 10k ? v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4) 1 ST7MC1/st7mc2 22/294 flash program memory (cont ? d) 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the spe- cific microcontroller device, the user needs only to implement the icp hardware interface on the ap- plication board (see figure 10 ). for more details on the pin locations, refer to the device pinout de- scription. 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase pro- tected to allow recovery in case errors occur dur- ing the programming operation. 4.7 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.8 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. 70 00000000 1 ST7MC1/st7mc2 23/294 5 supply, reset and clock management the device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 11 . for more details, refer to dedicated parametric section. main features reset sequence manager (rsm) 1 crystal/ceramic resonator oscillator system integrity management (si) ? main supply low voltage detection (lvd) ? auxiliary voltage detector (avd) with interrupt capability for monitoring the main supply ? clock security system (css) with the vco of the pll, providing a backup safe oscillator ? clock detector ? pll which can be used to multiply the fre- quency by 2 if the clock frequency input is 8mhz figure 11. clock, reset and supply block diagram low voltage detector (lvd) auxiliary voltage detector (avd) oscillator osc1 reset v ss v dd reset sequence manager (rsm) clock security system osc2 main clock css interrupt request avd interrupt request controller system watchdog sicsr, page 0 timer (wdg) with realtime clock (mcc/rtc) avd avd lvd rf css ie ie css d wdg rf f osc 0 f f cpu pa f mtc 1/2 safeosc 8mhz pll clock detector vco ck 0 en pa lo ck pll en sicsr, page 1 16mhz f osc cksel div2 opt lock ge 0 0 ge integrity management sel f clk 1 ST7MC1/st7mc2 24/294 5.1 oscillator the main clock of the st7 can be generated by a crystal or ceramic resonator oscillator or an exter- nal source. the associated hardware configurations are shown in table 4 . refer to the electrical character- istics section for more details. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is not connect- ed. crystal/ceramic oscillators this family of oscillators has the advantage of pro- ducing a very accurate rate on the main clock of the st7. in this mode, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. this oscillator is not stopped during the reset phase to avoid losing time in its start-up phase. see electrical characteristics for more details. table 4. st7 clock sources hardware configuration external clock crystal/ceramic resonators osc1 osc2 external st7 source nc osc1 osc2 load capacitors st7 c l2 c l1 1 ST7MC1/st7mc2 25/294 5.2 reset sequence manager (rsm) 5.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 13 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 12 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (selected by option byte) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. the reset vector fetch phase duration is 2 clock cycles. figure 12. reset sequence phases 5.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 14 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. figure 13. reset block diagram reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter 1 ST7MC1/st7mc2 26/294 reset sequence manager (cont ? d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 5.2.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 5.2.4 internal low voltage detector (lvd) reset two different reset s equences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop r eset the device reset pin acts as an output that is pulled low when v dd ST7MC1/st7mc2 28/294 system integrity management (cont ? d) 5.3.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply. the v it- reference value for falling voltage is lower than the v it+ reference value for rising volt- age in order to avoid parasitic detection (hystere- sis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd function is active only if the lvd is enabled through the option byte (see sec- tion 13.1 on page 284 ). 5.3.2.1 monitoring the v dd main supply if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit toggles). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 16 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over. if the voltage rise time t rv is less than 256 or 4096 cpu cycles (depending on the reset delay select- ed by option byte), no avd interrupt will be gener- ated when v it+(avd) is reached. if t rv is greater than 256 or 4096 cycles then: ? if the avd interrupt is enabled before the v it+(avd) threshold is reached, then 2 avd inter- rupts will be received: the first when the avdie bit is set, and the second when the threshold is reached. ? if the avd interrupt is enabled after the v it+(avd) threshold is reached then only one avd interrupt will occur. figure 16. using the avd to monitor v dd v dd v it+(avd) v it-(avd) avdf bit 0 0 1 if avdie bit = 1 v hyst avd interrupt request interrupt process interrupt process v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) t rv voltage rise time 1 ST7MC1/st7mc2 29/294 system integrity management (cont ? d) 5.3.3 clock security system (css) the clock security system (css) protects the st7 against main clock problems. to allow the in- tegration of the security features in the applica- tions, it is based on a pll which can provide a backup clock. the pll can be enabled or disabled by option byte or by software. it requires an 8-mhz input clock and provides a 16-mhz output clock. 5.3.3.1 safe oscillator control the safe oscillator of the css block is made of a pll. if the clock signal disappears (due to a broken or disconnected resonator...) the pll continues to provide a lower frequency, which allows the st7 to perform some rescue operations. automatically, the st7 clock source switches back from the safe oscillator if the original clock source recovers. 5.3.3.2 limitation detection the automatic safe oscillator selection is notified by hardware setting the cssd bit of the sicsr register. an interrupt can be generated if the cs- sie bit has been previously set. these two bits are described in the sicsr register description. 5.3.4 low power modes 5.3.4.1 interrupts the css or avd interrupt events generate an in- terrupt if the corresponding enable control bit (cssie or avdie) is set and the interrupt mask in the cc register is reset (rim instruction). note 1: this interrupt allows to exit from active- halt mode. mode description wait no effect on si. css and avd interrupts cause the device to exit from wait mode. halt the crsr register is frozen. the css (including the safe oscillator) is disabled until halt mode is exited. the previous css configuration resumes when the mcu is woken up by an interrupt with ? exit from halt mode ? capability or from the counter reset value when the mcu is woken up by a reset. the avd remains active, and an avd interrupt can be used to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt css event detection (safe oscillator acti- vated as main clock) cssd cssie yes no 1) avd event avdf avdie yes yes 1 ST7MC1/st7mc2 30/294 system integrity management (cont ? d) 5.3.5 register description system integrity (si) control/status register (sicsr, page 0) read/write reset value: 000x 000x (00h) bit 7 = page sicsr register page selection this bit selects the sicsr register page. it is set and cleared by software 0: access to sicsr register mapped in page 0. 1: access to sicsr register mapped in page 1. bit 6 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag changes (toggles). the pending interrupt informa- tion is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled bit 5 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the vdie bit is set, an interrupt request is gener- ated when the avdf bit changes value. 0: v dd over v it+ (avd) threshold 1: v dd under v it-(avd) threshold bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = reserved, must be kept cleared. bit 2 = cssie clock security syst . interrupt enable this bit enables the interrupt when a disturbance is detected by the clock security system (cssd bit set). it is set and cleared by software. 0: clock security system interrupt disabled 1: clock security system interrupt enabled when the pll is disabled (pllen=0), the cssie bit has no effect. bit 1 = cssd clock security system detection this bit indicates a disturbance on the main clock signal (f osc ): the clock stops (at least for a few cy- cles). it is set by hardware and cleared by reading the sicsr register when the original oscillator re- covers. 0: safe oscillator is not active 1: safe oscillator has been activated when the pll is disabled (pllen=0), the cssd bit value is forced to 0. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 70 pag e avd ie avd f lvd rf 0 css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x 1 ST7MC1/st7mc2 31/294 system integrity management (cont ? d) system integrity (si) control/status register (sicsr, page 1) reset value: 00000000 (00h) bit 7 = page sicsr register page selection this bit selects the sicsr register page. it is set and cleared by software 0: access to sicsr register mapped in page 0. 1: access to sicsr register mapped in page 1. bit 6 = reserved, must be kept cleared. bit 5 = vcoen vco enable this bit is set and cleared by software. 0: vco (voltage controlled oscillator) connected to the output of the pll charge pump (default mode), to obtain a 16-mhz output frequency (with an 8-mhz input frequency). 1: vco tied to ground in order to obtain a 10-mhz frequency (f vco ) notes: 1. during icc session, this bit is set to 1 in order to have an internal frequency which does not depend on the input clock. then, it can be reset in order to run faster with an external oscillator. bit 4 = lock pll locked this bit is read only. it is set by hardware. it is set automatically when the pll reaches its operating frequency. 0: pll not locked 1: pll locked bit 3 = pllen pll enable this bit enables the pll and the clock detector. it is set and cleared by software. 0: pll and clock detector (ckd) disabled 1: pll and clock detector (ckd) enabled notes: 1. during icc session, this bit is set to 1. 2. pll cannot be disabled if pll clock source is selected (cksel= 1). bit 2 = reserved, must be kept cleared. bit 1 = cksel clock source selection this bit selects the clock source: oscillator clock or clock from the pll. it is set and cleared by soft- ware. it can also be set by option byte (pll opt) 0: oscillator clock selected 1: pll clock selected notes: 1. during icc session, this bit is set to 1. then, cksel can be reset in order to run with f osc . 2. clock from the pll cannot be selected if the pll is disabled (pllen =0) 3. if the clock source is selected by pll option bit, cksel bit selection has no effect. bit 0 = reserved, must be kept cleared. 70 pa ge 0 vco en lo ck pll en 0 ck- sel 0 1 ST7MC1/st7mc2 32/294 5.4 main clock controller with real time clock and beeper (mcc/rtc) the main clock controller consists of three differ- ent functions: a programmable cpu clock prescaler a clock-out signal to supply external devices a real time clock timer with interrupt capability each function can be used independently and si- multaneously. 5.4.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal periph- erals. it manages slow power saving mode (see section 7.2 slow mode for more details). the prescaler selects the f cpu main clock frequen- cy and is controlled by three bits in the mccsr register: cp[1:0] and sms. 5.4.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc2 clock to drive external devices. it is controlled by the mco bit in the mccsr register. caution : when selected, the clock out pin sus- pends the clock during active-halt mode. 5.4.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc2 are available. the whole functionality is controlled by four bits of the mcc- sr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 7.4 ac- tive-halt and halt modes for more details. 5.4.4 beeper the beep function is controlled by the mccbcr register. it can output three selectable frequencies on the beep pin (i/o port alternate function). figure 17. main clock controller (mcc/rtc) block diagram div 2, 4, 8, 16 mcc/rtc interrupt sms div128 cp0 tb1 tb0 oie oif cpu clock mccsr rtc counter to cpu and peripherals f osc2 f cpu mco mco bc1 bc0 mccbcr beep generator beep signal to motor control peripheral f mtc (and to mtc peripheral) div 2, 4, 8, 16 div 2 f clk div 2 f adc 1 ST7MC1/st7mc2 33/294 main clock controller with real time clock (cont ? d) 5.4.5 low power modes 5.4.6 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : the mcc/rtc interrupt wakes up the mcu from active-halt mode, not from halt mode. 5.4.7 register description mcc control/status register (mccsr) read/write reset value: 0000 0000 (00h ) bit 7 = mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc2 on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 6:5 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 4 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc2 1: slow mode. f cpu is given by cp1, cp0 see section 7.2 slow mode and section 5.4 main clock controller with real time clock and beeper (mcc/rtc) for more de- tails. bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active- halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with ? exit from halt ? capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) 70 mco cp1 cp0 sms tb1 tb0 oie oif f cpu in slow mode cp1 cp0 f osc2 / 2 0 0 f osc2 / 4 0 1 f osc2 / 8 1 0 f osc2 / 16 1 1 counter prescaler time base tb1 tb0 f osc2 =4mhz f osc2 =8mhz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 1 ST7MC1/st7mc2 34/294 main clock controller with real time clock (cont ? d) bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. mcc beep control register (mccbcr) read/write reset value: 0000 0000 (00h) bit 7:4 = reserved, must be kept cleared. bit 3 = adsts a/d converter sample time stretch this bit is set and cleared by software to enable or disable the a/d converter sample time stretch fea- ture. 0: ad sample time stretch disabled (for standard impedance analog inputs) 1 ad sample time stretch enabled (for high imped- ance analog inputs) bit 2 = adcie a/d converter interrupt enable this bit is set and cleared by software to enable or disable the a/d converter interrupt. 0: ad interrupt disabled 1 ad interrupt enabled bit 1:0 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. table 5. main clock controller register map and reset values 70 0000 ad- sts adc ie bc1 bc0 bc1 bc0 beep mode with f osc2 =8mhz 00 off 01 ~2-khz output beep signal ~50% duty cycle 10 ~1-khz 1 1 ~500-hz address (hex.) register label 76543210 0040h sicsr, page0 reset value page 0 vdie 0 vdf 0 lvdrf x0 cfie 0 cssd 0 wdgrf x 0040h sicsr, page1 reset value page 00 vcoen 0 lock x pllen 00 cksel 00 002ch mccsr reset value mco 0 cp1 0 cp0 0 sms 0 tb1 0 tb0 0 oie 0 oif 0 002dh mccbcr reset value0000 adsts 0 adcie 0 bc1 0 bc0 0 1 ST7MC1/st7mc2 35/294 6 interrupts 6.1 introduction the st7 enhanced interrupt management pro- vides the following features: hardware interrupts software interrupt (trap) nested or concurrent interrupt management with flexible interrupt priority and level management: ? up to 4 software programmable nesting levels ? up to 16 interrupt vectors fixed by hardware ? 2 non maskable events: r eset, trap ? 1 maskable top level event: mces this interrupt management is based on: ? bit 5 and bit 3 of the cpu cc register (i1:0), ? interrupt software priority registers (isprx), ? fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) st7 interrupt controller. 6.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 6 ). the process- ing flow is shown in figure 18 when an interrupt request has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ? interrupt mapping ? table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 6. interrupt software priority levels figure 18. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ? iret ? restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset mces pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt 1 ST7MC1/st7mc2 36/294 interrupts (cont ? d) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: ? the highest software priority interrupt is serviced, ? if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 19 describes this decision process. figure 19. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and mces can be consid- ered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, trap) and the maskable type (external or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 18 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 18 as a mces top level interrupt. reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. mces (mtc emergency stop) this hardware interrupt occurs when a specific edge is detected on the dedicated mces pin or when an error is detected by the micro in the motor speed measurement. external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ? interrupt mapping ? table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced 1 ST7MC1/st7mc2 37/294 interrupts (cont ? d) 6.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column ? exit from halt ? in ? interrupt mapping ? table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision proc- ess shown in figure 19 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 6.4 concurrent & nested management the following figure 20 and figure 21 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 21 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, mces. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 20. concurrent interrupt management figure 21. nested interrupt management main it4 it2 it1 mces it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 mces it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 mces main it0 it2 it1 it4 mces it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes 1 ST7MC1/st7mc2 38/294 interrupts (cont ? d) 6.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see ? interrupt dedicated instruction set ? table). *note : mces, trap and reset events can in- terrupt a level 3 program. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. ? each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. ? each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. ? level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and mces vectors have no software priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the mces can be read and written but they are not significant in the interrupt process management. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits 1 ST7MC1/st7mc2 39/294 interrupts (cont ? d) table 7. dedicated interrupt instruction set note : during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 (level 3) i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 1 ST7MC1/st7mc2 40/294 interrupts (cont ? d) table 8. interrupt mapping note 1. valid for halt and active-halt modes except for the mcc/rtc or css interrupt source which exits from active-halt mode only. n source block description register label priority order exit from halt 1) address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0mces motor control emergency stop or speed error interrupt misr mcrc no fffah-fffbh 1 mcc/rtc css main clock controller time base interrupt safe oscillator activation interrupt mccsr sicsr yes fff8h-fff9h 2 ei0 external interrupt port n/a yes fff6h-fff7h 3 ei1 external interrupt port yes fff4h-fff5h 4 ei2 external interrupt port yes fff2h-fff3h 5 mtc event u or current loop or sampling out misr no fff0h-fff1h 6 event r or event z no ffeeh-ffefh 7 event c or event d no ffech-ffedh 8 spi spi peripheral interrupts spicsr yes ffeah-ffebh 9 timer a timer a peripheral interrupts tasr no ffe8h-ffe9h 10 timer b timer b peripheral interrupts tbsr no ffe6h-ffe7h 11 lin sci ? lin sci ? peripheral interrupts scisr no ffe4h-ffe5h 12 avd/ adc auxiliary voltage detector interrupt adc end of conversion interrupt sicsr adcsr yes ffe2h-ffe3h 13 pwm art pwm art overflow interrupt artcsr no ffe0h-ffe1h 1 ST7MC1/st7mc2 41/294 interrupts (cont ? d) 6.6 external interrupts the pending interrupts are cleared writing a differ- ent value in the isx[1:0], ipa or ipb bits of the eicr. note: external interrupts are masked when an i/o (configured as input interrupt) of the same inter- rupt vector is forced to v ss . 6.6.1 i/o port interrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the eicr register ( figure 22 ). this control allows to have up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: falling edge rising edge falling and rising edge falling edge and low level rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the eicr register can be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). 1 ST7MC1/st7mc2 42/294 interrupts (cont ? d) figure 22. external interrupt control bits is20 is21 eicr sensitivity control paor.7 paddr.7 pa7 ei1 interrupt source port a [7:3] interrupts pa7 pa6 pa5 pa3 is10 is11 eicr sensitivity control pcor.0 pcddr.0 pc0 ei2 interrupt source port c0, pb[7:6] interrupts pc0 pb7 pb6 is30 is31 eicr sensitivity control pdor.6 pdddr.6 ipa bit pd6 ei0 interrupt source port d [6:4] interrupts pd6 pd5 pd4 is30 is31 eicr sensitivity control pdor.3 pdddr.3 pd3 ei0 interrupt source port d [3:1] interrupts pd3 pd2 pd1 is10 is11 eicr sensitivity control pcor.3 pcddr.3 ipb bit pc3 ei2 interrupt source port c [3:1] interrupts pc3 pc2 pc1 1 ST7MC1/st7mc2 43/294 interrupts (cont ? d) 6.7 external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 (port c3..1) - ei2 (port c0, b7..6) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = ipb interrupt polarity for port c this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion bit 4:3= is2[1:0] ei1sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei1 (port a3, a5...a7) bit 2:1= is3[1:0] ei0sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: 70 is11 is10 ipb is21 is20 is31 is30 ipa is11 is10 external interrupt sensitivity ipb bit =0 ipb bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 1 ST7MC1/st7mc2 44/294 external interrupt control register (eicr) (cont ? d) - ei0 (port d5..3) - ei0 (port d2..0) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 0= ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it can be set and cleared by software only when i1 and i0 of the cc register are both set to 1 (level 3). 0: no sensitivity inversion 1: sensitivity inversion is31 is30 external interrupt sensitivity ipa bit =0 ipa bit =1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is31 is30 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 1 ST7MC1/st7mc2 45/294 interrupts (cont ? d) table 9. nested interrupts register map and reset values address (hex.) register label 76543210 0024h ispr0 reset value ei1 ei0 mcc + si mces i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value mtc c/d mtc r/z mtc u/cl ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value sci timer b timer a spi i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value pwmart avd i1_15 1 i0_15 1 i1_14 1 i0_14 1 i1_13 1 i0_13 1 i1_12 1 i0_12 1 0028h eicr reset value is11 0 is10 0 ipb 0 is21 0 is20 0 ipa 0 00 1 ST7MC1/st7mc2 46/294 7 power saving modes 7.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 23 ): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. figure 23. power saving mode transitions 7.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by three bits in the mccsr register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the master clock frequency (f osc2 ) can be divided by 2, 4, 8 or 16. the cpu and pe- ripherals are clocked at this lower frequency (f cpu ). note : slow-wait mode is activated when enter- ing the wait mode while the device is already in slow mode. figure 24. slow mode clock transitions power consumption wait slow run active halt high low slow wait halt 00 01 sms cp1:0 f cpu new slow normal run mode mccsr frequency request request f osc2 f osc2 /2 f osc2 /4 f osc2 1 ST7MC1/st7mc2 47/294 power saving modes (cont ? d) 7.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ? wfi ? instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to ? 10 ? , to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 25 . figure 25. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 256 or 4096 cpu clock cycle delay 1 ST7MC1/st7mc2 48/294 power saving modes (cont ? d) 7.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the ? halt ? instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 7.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ? halt ? in- struction when the oie bit of the main clock con- troller status register (mccsr) is set (see section 5.4 on page 32 for more details on the mccsr register). the mcu can exit active-halt mode on recep- tion of either an mcc/rtc interrupt, a specific in- terrupt (see table 8, ? interrupt mapping, ? on page 40) or a reset. when exiting active- halt mode by means of an interrupt, no 256 or 4096 cpu cycle delay occurs. the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 27 ). when entering active-halt mode, the i[1:0] bits in the cc register are forced to ? 10b ? to enable in- terrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 26. active-halt timing overview figure 27. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripheral clocked with an external clock source can still be active. 3. only the mcc/rtc interrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 8, ? interrupt mapping, ? on page 40 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and restored when the cc register is popped. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock cycle delay (mccsr.oie=1) 1 ST7MC1/st7mc2 49/294 power saving modes (cont ? d) 7.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ? halt ? instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 5.4 on page 32 for more de- tails on the mccsr register). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 8, ? interrupt mapping, ? on page 40) or a r eset. w hen exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 29 ). when entering halt mode, the i[1:0] bits in the cc register are forced to ? 10b ? to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the ? wdghalt ? op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 13.1 on page 284 for more details). figure 28. halt timing overview figure 29. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 8, ? interrupt mapping, ? on page 40 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (mccsr.oie=0) cycle 1 ST7MC1/st7mc2 50/294 8 i/o ports 8.1 introduction the i/o ports offer different functional modes: ? transfer of data through digital inputs and outputs and for specific pins: ? external interrupt generation ? alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 functional description each port has 2 main registers: ? data register (dr) ? data direction register (ddr) and one optional register: ? option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 30 8.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. do not use read/modify/write instructions (bset or bres) to modify the dr register external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the eicr register and then logically ored. the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the eicr register must be modified. 8.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 8.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pull open-drain 0v ss vss 1v dd floating 1 ST7MC1/st7mc2 51/294 i/o ports (cont ? d) figure 30. i/o port general block diagram table 10. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) external source (ei x ) interrupt cmos schmitt trigger register access 1 ST7MC1/st7mc2 52/294 i/o ports (cont ? d) table 11. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interrupt data bus pull-up interrupt dr register access w r source (ei x ) dr register condition alternate input not implemented in true open drain i/o ports analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register not implemented in true open drain i/o ports 1 ST7MC1/st7mc2 53/294 i/o ports (cont ? d) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 8.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 31 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 8.4 low power modes 8.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or 1 ST7MC1/st7mc2 54/294 i/o ports (cont ? d) 8.5.1 i/o port implementation the i/o port register configurations are summa- rised as follows. standard ports pa4, pa2:0, pb5:0, pc7:4, pd7:6, pe5:0, pf5:0, pg7:0, ph7:0 interrupt ports pa6, pa3, pb6, pc3, pc1, pd5, pd4, pd2 (with pull-up) pa7, pa5, pb7, pc2, pc0, pd6, pd3, pd1 (with- out pull-up) table 12. port configuration mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7, pa5 floating floating interrupt open drain push-pull pa6, pa3 floating pull-up interrupt open drain push-pull pa2:0 floating pull-up open drain push-pull port b pb7 floating floating interrupt open drain push-pull pb6 floating pull-up interrupt open drain push-pull pb5:0 floating pull-up open drain push-pull port c pc7:4 floating pull-up open drain push-pull pc3, pc1 floating pull-up interrupt open drain push-pull pc2, pc0 floating floating interrupt open drain push-pull port d pd7, pd0 floating pull-up open drain push-pull pd6, pd3, pd1 floating floating interrupt open drain push-pull pd5, pd4, pd2 floating pull-up interrupt open drain push-pull port e pe5:0 floating pull-up open drain push-pull port f pf5:0 floating pull-up open drain push-pull port g pg7:0 floating pull-up open drain push-pull port h ph7:0 floating pull-up open drain push-pull 1 ST7MC1/st7mc2 55/294 i/o ports (cont ? d) table 13. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0003h pbdr msb lsb 0004h pbddr 0005h pbor 0006h pcdr msb lsb 0007h pcddr 0008h pcor 0009h pddr msb lsb 000ah pdddr 000bh pdor 000ch pedr msb lsb 000dh peddr 000eh peor 000fh pfdr msb lsb 0010h pfddr 0011h pfor 0012h pgdr msb lsb 0013h pgddr 0014h pgor 0015h phdr msb lsb 0016h phddr 0017h phor 1 ST7MC1/st7mc2 56/294 9 on-chip peripherals 9.1 window watchdog (wwdg) 9.1.1 introduction the window watchdog is used to detect the oc- currence of a software fault, usually generated by external interference or by unforeseen logical con- ditions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the contents of the downcounter before the t6 bit becomes cleared. an mcu reset is also gener- ated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. this implies that the counter must be refreshed in a limited win- dow. 9.1.2 main features ? programmable free-running downcounter ? conditional reset ? reset (if watchdog activated) when the down- counter value becomes less than 40h ? reset (if watchdog activated) if the down- counter is reloaded outside the window (see figure 35 ) ? hardware/software watchdog activation (se- lectable by option byte) ? optional reset on halt instruction (configurable by option byte) 9.1.3 functional description the counter value stored in the wdgcr register (bits t[6:0]), is decremented every 16384 f osc2 cycles (approx.), and the length of the timeout pe- riod can be programmed by the user in 64 incre- ments. if the watchdog is activated (the wdga bit is set) and when the 7-bit downcounter (t[6:0] bits) rolls over from 40h to 3fh (t6 becomes cleared), it ini- tiates a reset cycle pulling low the reset pin for typ- ically 30 s. if the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. figure 32. watchdog block diagram reset wdga 6-bit downcounter (cnt) t6 t0 watchdog control register (wdgcr) t1 t2 t3 t4 t5 - w6 w0 watchdog window register (wdgwr) w1 w2 w3 w4 w5 comparator t6:0 > w6:0 cmp =1 when write wdgcr wdg prescaler div 4 f osc2 12-bit mcc rtc counter msb lsb div 64 0 5 6 11 mcc/rtc tb[1:0] bits (mccsr register) 1 ST7MC1/st7mc2 57/294 window watchdog (cont ? d) the application program must write in the wdgcr register at regular intervals during normal operation to prevent an mcu reset. this operation must occur only when the counter value is lower than the window register value. the value to be stored in the wdgcr register must be between ffh and c0h (see figure 33 ): ? enabling the watchdog: when software watchdog is selected (by option byte), the watchdog is disabled after a reset. it is enabled by setting the wdga bit in the wdgcr register, then it cannot be disabled again except by a reset. when hardware watchdog is selected (by option byte), the watchdog is always active and the wdga bit is not used. ? controlling the downcounter : this downcounter is free-running: it counts down even if the watchdog is disabled. when the watchdog is enabled, the t6 bit must be set to prevent generating an immediate reset. the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see figure 33. ap- proximate timeout duration ). the timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writ- ing to the wdgcr register (see figure 34 ). the window register (wdgwr) contains the high limit of the window: to prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3fh. figure 35 describes the window watch- dog process. note: the t6 bit can be used to generate a soft- ware reset (the wdga bit is set and the t6 bit is cleared). ? watchdog reset on halt option if the watchdog is activated and the watchdog re- set on halt option is selected, then the halt in- struction will generate a reset. 9.1.4 using halt mode with the wdg if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruc- tion to refresh the wdg counter, to avoid an unex- pected wdg reset immediately after waking up the microcontroller. 1 ST7MC1/st7mc2 58/294 window watchdog (cont ? d) 9.1.5 how to program the watchdog timeout figure 33 shows the linear relationship between the 6-bit value to be loaded in the watchdog coun- ter (cnt) and the resulting timeout duration in mil- liseconds. this can be used for a quick calculation without taking the timing variations into account. if more precision is needed, use the formulae in fig- ure 34 . caution: when writing to the wdgcr register, al- ways write 1 in the t6 bit to avoid generating an immediate reset. figure 33. approximate timeout duration cnt value (hex.) watchdog timeout (ms) @ 8 mhz. f osc2 3f 00 38 128 1.5 65 30 28 20 18 10 08 50 34 18 82 98 114 1 ST7MC1/st7mc2 59/294 watchdog timer (cont ? d) figure 34. exact timeout duration (t min and t max ) where : t min0 = (lsb + 128) x 64 x t osc2 t max0 = 16384 x t osc2 t osc2 = 125ns if f osc2 =8 mhz cnt = value of t[5:0] bits in the wdgcr register (6 bits) msb and lsb are values from the table below depending on the timebase selected by the tb[1:0] bits in the mccsr register to calculate the minimum watchdog timeout (t min ): if then else to calculate the maximum watchdog timeout (t max ): if then else note: in the above formulae, division results must be rounded down to the next integer value. example: with 2ms timeout selected in mccsr register tb1 bit (mccsr reg.) tb0 bit (mccsr reg.) selected mccsr timebase msb lsb 0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54 value of t[5:0] bits in wdgcr register (hex.) min. watchdog timeout (ms) t min max. watchdog timeout (ms) t max 00 1.496 2.048 3f 128 128.552 cnt msb 4 ------------- < t min t min0 16384 cnt t osc2 + = t min t min0 16384 cn t 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = cnt msb 4 ------------- t max t max0 16384 cnt t osc2 + = t max t max0 16384 c nt 4cnt msb ---------------- - ? ?? ?? 192 lsb + () 64 4cnt msb ---------------- - + t osc2 + = 1 ST7MC1/st7mc2 60/294 window watchdog (cont ? d) figure 35. window watchdog timing diagram 9.1.6 low power modes 9.1.7 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the wdgcr is not used. refer to the option byte description. 9.1.8 using halt mode with the wdg (wdghalt option) the following recommendation applies if halt mode is used when the watchdog is enabled. ? before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. t6 bit reset wdgwr t[5:0] cnt downcounter time refresh window refresh not allowed (step = 16384/f osc2 ) 3fh mode description slow no effect on watchdog : the downcounter continues to decrement at normal speed. wait no effect on watchdog : the downcounter continues to decrement. halt oie bit in mccsr register wdghalt bit in option byte 00 no watchdog reset is generated. the mcu enters halt mode. the watch- dog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the mcu receives an external inter- rupt or a reset. if an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the watchdog restarts counting after 256 or 4096 cpu clocks. if a reset is generated, the watchdog is disabled (reset state) unless hardware watchdog is selected by option byte. for applica- tion recommendations see section 9.1.8 below. 0 1 a reset is generated instead of entering halt mode. active halt 1x no reset is generated. the mcu enters active halt mode. the watchdog counter is not decremented. it stop counting. when the mcu receives an oscillator interrupt or external interrupt, the watchdog restarts counting im- mediately. when the mcu receives a reset the watchdog restarts counting after 256 or 4096 cpu clocks. 1 ST7MC1/st7mc2 61/294 window watchdog (cont ? d) 9.1.9 interrupts none. 9.1.10 register description control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit. this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit counter (msb to lsb) . these bits contain the value of the watchdog counter. it is decremented every 16384 f osc2 cy- cles (approx.). a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). window register (wdgwr) read/write reset value: 0111 1111 (7fh) bit 7 = reserved bits 6:0 = w[6:0] 7-bit window value these bits contain the window value to be com- pared to the downcounter. 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - w6w5w4w3w2w1w0 1 ST7MC1/st7mc2 62/294 table 14. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 002bh wdgwr reset value 0 0 w6 1 w5 1 w4 1 w3 1 w2 1 w1 1 w0 1 1 ST7MC1/st7mc2 63/294 9.2 pwm auto-reload timer (art) 9.2.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. these resources allow five possible operating modes: ? generation of up to 4 independent pwm signals ? output compare and time base interrupt ? up to two input capture functions ? external event detector ? up to two external interrupt sources the three first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 36. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port function alternate ocrx compare register programmable prescaler 8-bit counter (car register) arr register icrx register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext articx icfx icsx iccsr load icx interrupt iciex input capture control 1 ST7MC1/st7mc2 64/294 pwm auto-reload timer (cont ? d) 9.2.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (artcar). when a counter overflow occurs, the counter is automatically reloaded with the contents of the artarr register (the prescaler is not affected). counter clock and prescaler the counter clock frequency is given by: f counter = f input / 2 cc[2:0] the timer counter ? s input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (artcsr). thus the division factor of the prescal- er can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the artcsr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the artcsr register. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input = f cpu . the counter can be initialized by: ? writing to the artarr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the artcsr reg- ister. ? writing to the artcar counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the prescaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (pwmdcrx) at each overflow of the counter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 37. output compare control counter fdh feh ffh fdh feh ffh fdh feh artarr=fdh f counter ocrx pwmdcrx fdh feh fdh feh ffh pwmx 1 ST7MC1/st7mc2 65/294 pwm auto-reload timer (cont ? d) independent pwm signal generation this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the artarr register value. f pwm = f counter / (256 - artarr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the artarr reg- ister. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - artarr) note : to get the maximum resolution (1/256), the artarr register must be 0. with this maximum resolution, 0% and 100% can be obtained by changing the polarity. figure 38. pwm auto-reload timer function figure 39. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (artarr) (pwmdcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh artarr=fdh f counter 1 ST7MC1/st7mc2 66/294 pwm auto-reload timer (cont ? d) output compare and time base interrupt on overflow, the ovf flag of the artcsr register is set and an overflow interrupt request is generat- ed if the overflow interrupt enable bit, oie, in the artcsr register, is set. the ovf flag must be re- set by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the artarr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - artarr caution: the external clock function is not availa- ble in halt mode. if halt mode is used in the ap- plication, prior to executing the halt instruction, the counter must be disabled by clearing the tce bit in the artcsr register to avoid spurious coun- ter increments. figure 40. external event detector example (3 counts) counter t fdh feh ffh fdh ovf artcsr read interrupt artarr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 artcsr read 1 ST7MC1/st7mc2 67/294 pwm auto-reload timer (cont ? d) input capture function this mode allows the measurement of external signal pulse widths through articrx registers. each input capture can generate an interrupt inde- pendently on a selected input signal transition. this event is flagged by a set of the corresponding cfx bits of the input capture control/status regis- ter (articcsr). these input capture interrupts are enabled through the ciex bits of the articcsr register. the active transition (falling or rising edge) is soft- ware programmable through the csx bits of the articcsr register. the read only input capture registers (articrx) are used to latch the auto-reload counter value when a transition is detected on the articx pin (cfx bit set in articcsr register). after fetching the interrupt vector, the cfx flags can be read to identify the interrupt source. note : after a capture detection, data transfer in the articrx register is inhibited until it is read (clearing the cfx bit). the timer interrupt remains pending while the cfx flag is set when the interrupt is enabled (ciex bit set). this means, the articrx register has to be read at each capture event to clear the cfx flag. the timing resolution is given by auto-reload coun- ter cycle time (1/f counter ). note: during halt mode, if both input capture and external clock are enabled, the articrx reg- ister value is not guaranteed if the input capture pin and the external clock change simultaneously. external interrupt capability this mode allows the input capture capabilities to be used as external interrupt sources. the inter- rupts are generated on the edge of the articx signal. the edge sensitivity of the external interrupts is programmable (csx bit of articcsr register) and they are independently enabled through ciex bits of the articcsr register. after fetching the interrupt vector, the cfx flags can be read to iden- tify the interrupt source. during halt mode, the external interrupts can be used to wake up the micro (if the ciex bit is set). figure 41. input capture timing diagram 04h counter t 01h f counter xxh 02h 03h 05h 06h 07h 04h articx pin cfx flag icrx register interrupt 1 ST7MC1/st7mc2 68/294 pwm auto-reload timer (cont ? d) 9.2.3 register description control / status register (artcsr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of artarr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the artcsr register. it indicates the tran- sition of the counter from ffh to the artarr val- ue . 0: new transition not yet reached 1: transition reached counter access register (artcar) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the artcar register is used to read or write the auto-reload counter ? on the fly ? (while it is counting). auto-reload register (artarr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: ? adjusting the pwm frequency ? setting the pwm duty cycle resolution pwm frequency vs. resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input / 2 f input / 4 f input / 8 f input / 16 f input / 32 f input / 64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7ca6ca5ca4ca3ca2ca1ca0 70 ar7ar6ar5ar4ar3ar2ar1ar0 artarr value resolution f pwm min max 0 8-bit ~0.244-khz 31.25-khz [ 0..127 ] > 7-bit ~0.244-khz 62.5-khz [ 128..191 ] > 6-bit ~0.488-khz 125-khz [ 192..223 ] > 5-bit ~0.977-khz 250-khz [ 224..239 ] > 4-bit ~1.953-khz 500-khz 1 ST7MC1/st7mc2 69/294 pwm auto-reload timer (cont ? d) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:4 = oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:0 = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals. note : when an opx bit is modified, the pwmx out- put signal polarity is immediately reversed. duty cycle registers (pwmdcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a pwmdcrx register is associated with the ocrx register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all channels and given by the artarr register). these pwmdcr regis- ters allow the duty cycle to be set independently for each pwm channel. 70 oe3 oe2 oe1 oe0 op3 op2 op1 op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 1 ST7MC1/st7mc2 70/294 pwm auto-reload timer (cont ? d) input capture control / status register (articcsr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved, always read as 0. bit 5:4 = cs[2:1] capture sensitivity these bits are set and cleared by software. they determine the trigger event polarity on the corre- sponding input capture channel. 0: falling edge triggers capture on channel x. 1: rising edge triggers capture on channel x. bit 3:2 = cie[2:1] capture interrupt enable these bits are set and cleared by software. they enable or disable the input capture channel inter- rupts independently. 0: input capture channel x interrupt disabled. 1: input capture channel x interrupt enabled. bit 1:0 = cf[2:1] capture flag these bits are set by hardware and cleared by software reading the corresponding articrx reg- ister. each cfx bit indicates that an input capture x has occurred. 0: no input capture on channel x. 1: an input capture has occured on channel x. input capture registers (articrx) read only reset value: 0000 0000 (00h) bit 7:0 = ic[7:0] input capture data these read only bits are set and cleared by hard- ware. an articrx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event. 70 0 0 cs2 cs1 cie2 cie1 cf2 cf1 70 ic7ic6ic5ic4ic3ic2ic1ic0 1 ST7MC1/st7mc2 71/294 pwm auto-reload timer (cont ? d) table 15. pwm auto-reload timer register map and reset values address (hex.) register label 76543210 0073h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0074h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0077h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0078h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 oie 0 ovf 0 0079h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 007ah artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 007bh articcsr reset value 00 cs2 0 cs1 0 cie2 0 cie1 0 cf2 0 cf1 0 007ch articr1 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 007dh articr2 reset value ic7 0 ic6 0 ic5 0 ic4 0 ic3 0 ic2 0 ic1 0 ic0 0 1 ST7MC1/st7mc2 72/294 9.3 16-bit timer 9.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some devices of the st7 family have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are syn- chronized after a device reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in the devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 9.3.2 main features programmable prescaler: f cpu divided by 2, 4 or 8. overflow status flag and maskable interrupt external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge output compare functions with ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt input capture functions with ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 42 . *note: some timer pins may not available (not bonded) in some devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be ? 1 ? . 9.3.3 functional description 9.3.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): ? counter high register (chr) is the most sig- nificant byte (ms byte). ? counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) ? alternate counter high register (achr) is the most significant byte (ms byte). ? alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 16 clock control bits . the value in the counter register re- peats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency. 1 ST7MC1/st7mc2 73/294 16-bit timer (cont ? d) figure 42. timer block diagram 16-bit timer peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note) csr 1 ST7MC1/st7mc2 74/294 16-bit timer (cont ? d) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: ? the tof bit of the sr register is set. ? a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (device awakened by an interrupt) or from the reset count (device awakened by a reset). 9.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + ? t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte 1 ST7MC1/st7mc2 75/294 16-bit timer (cont ? d) figure 43. counter timing diagram, internal clock divided by 2 figure 44. counter timing diagram, internal clock divided by 4 figure 45. counter timing diagram, internal clock divided by 8 note: the device is in reset state when the internal reset signal is high, when it is low the device is run- ning. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 1 ST7MC1/st7mc2 76/294 16-bit timer (cont ? d) 9.3.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: ? select the timer clock (cc[1:0]) (see table 16 clock control bits ). ? select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). and select the following in the cr1 register: ? set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: ? icf i bit is set. ? the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 47 ). ? a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr 1 ST7MC1/st7mc2 77/294 16-bit timer (cont ? d) figure 46. input capture block diagram figure 47. input capture timing diagram note: the time between an event on the icapi pin and the appearance of the corresponding flag is from 2 to 3 cpu clock cycles. this depends on the moment when the icap event happens relative to the timer clock. icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: the active edge is the rising edge. 1 ST7MC1/st7mc2 78/294 16-bit timer (cont ? d) 9.3.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: ? assigns pins with a programmable value if the ocie bit is set ? sets a flag in the status register ? generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: ? set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. ? select the timer clock (cc[1:0]) (see table 16 clock control bits ). and select the following in the cr1 register: ? select the olvl i bit to applied to the ocmp i pins after the match occurs. ? set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ? ocf i bit is set. ? the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). ? a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: ? t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 16 clock control bits ) if the timer clock is an external clock, the formula is: where: ? t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: ? write to the oc i hr register (further compares are inhibited). ? read the sr register (first step of the clearance of the ocf i bit, which may be already set). ? write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr ? oc i r = ? t * f cpu presc ? oc i r = ? t * f ext 1 ST7MC1/st7mc2 79/294 16-bit timer (cont ? d) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 49 on page 80 ). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 50 on page 80 ). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one pulse mode and pwm mode. figure 48. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 1 ST7MC1/st7mc2 80/294 16-bit timer (cont ? d) figure 49. output compare timing diagram, f timer =f cpu /2 figure 50. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i ) 1 ST7MC1/st7mc2 81/294 16-bit timer (cont ? d) 9.3.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see table 16 clock control bits ). when a valid event occurs on the icap1 pin, the counter value is loaded in the icr1 register. the counter is then initialized to fffch, the olvl2 bit is output on the ocmp1 pin and the icf1 bit is set. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 16 clock control bits ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 51 ). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 1 ST7MC1/st7mc2 82/294 16-bit timer (cont ? d) figure 51. one pulse mode timing example figure 52. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 01f8 01f8 2ed3 ic1r counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2 1 ST7MC1/st7mc2 83/294 16-bit timer (cont ? d) 9.3.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r regis- ter, and so this functionality can not be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values writ- ten in the oc1r and oc2r registers are loaded in their respective shadow registers (double buffer) only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). the shadow registers contain the reference values for comparison in pwm ? double buffering ? mode. note: there is a locking mechanism for transfer- ring the ocir value to the buffer. after a write to the ocihr register, transfer of the new compare value to the buffer is inhibited until ocilr is also written. unlike in output compare mode, the compare function is always enabled in pwm mode. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1=0 and olvl2=1) using the formula in the oppo- site column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. ? using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see table 16 clock control bits ). if olvl1=1 and olvl2=0 the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 16 clock control bits ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 52 ) notes: 1. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 2. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 1 ST7MC1/st7mc2 84/294 16-bit timer (cont ? d) 3. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 4. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 9.3.4 low power modes 9.3.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 9.3.6 summary of timer modes 1) see note 4 in section 9.3.3.5 one pulse mode 2) see note 5 in section 9.3.3.5 one pulse mode 3) see note 4 in section 9.3.3.6 pulse width modulation mode mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the device is woken up by an interrupt with ? exit from halt mode ? capability or from the counter reset value when the device is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the device is woken up by an interrupt with ? exit from halt mode ? capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no 1 ST7MC1/st7mc2 85/294 16-bit timer (cont ? d) 9.3.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 1 ST7MC1/st7mc2 86/294 16-bit timer (cont ? d) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 16. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 0 1 f cpu / 8 1 0 external clock (where available) 11 1 ST7MC1/st7mc2 87/294 16-bit timer (cont ? d) control/status register (csr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2 = timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disa- bled the output functions (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled bits 1:0 = reserved, must be kept cleared. 70 icf1 ocf1 tof icf2 ocf2 timd 0 0 1 ST7MC1/st7mc2 88/294 16-bit timer (cont ? d) input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 1 ST7MC1/st7mc2 89/294 16-bit timer (cont ? d) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 1 ST7MC1/st7mc2 90/294 16-bit timer (cont ? d) table 17. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 csr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 timd 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb - 1 ST7MC1/st7mc2 91/294 9.4 serial peripheral interface (spi) 9.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 9.4.2 main features full duplex synchronous transfers (on 3 lines) simplex synchronous transfers (on 2 lines) master or slave operation six master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 9.4.3 general description figure 53 shows the serial peripheral interface (spi) block diagram. there are 3 registers: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through 4 pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves ? ss : slave select: this input signal acts as a ? chip select ? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master device . 1 ST7MC1/st7mc2 92/294 figure 53. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 1 ST7MC1/st7mc2 93/294 serial peripheral interface (cont ? d) 9.4.3.1 functional description a basic example of interconnections between a single master and a single slave is illustrated in figure 54 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is always initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this implies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node ( in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 57 ) but master and slave must be programmed with the same timing mode. figure 54. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1 ST7MC1/st7mc2 94/294 serial peripheral interface (cont ? d) 9.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 56 ) in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ? ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 55 ): if cpha=1 (data latched on 2nd clock edge): ? ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm= 1 and ssi=0 in the in the spicsr register) if cpha=0 (data latched on 1st clock edge): ? ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 9.4.5.3 ). figure 55. generic ss timing diagram figure 56. hardware/software slave select management mosi/miso master ss slave ss (if cpha=0) slave ss (if cpha=1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1 ST7MC1/st7mc2 95/294 serial peripheral interface (cont ? d) 9.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). to operate the spi in master mode, perform the following steps in order (if the spicsr register is not written first, the spicr register setting (mstr bit ) may be not taken into account): 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 57 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). the transmit sequence begins when software writes a byte in the spidr register. 9.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 9.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 57 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 9.4.3.2 and figure 55 . if cpha=1 ss must be held low continuously. if cpha=0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to e nable the spi i/o functions. 9.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set. 2. a write or a read to the spidr register. notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 9.4.5.2 ). 1 ST7MC1/st7mc2 96/294 serial peripheral interface (cont ? d) 9.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 57 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol=1 or pulling down sck if cpol=0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge figure 57 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 57. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) 1 ST7MC1/st7mc2 97/294 serial peripheral interface (cont ? d) 9.4.5 error flags 9.4.5.1 master mode fault (modf) master mode fault occurs when the master device has its ss pin pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multi master configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application de- fault state. 9.4.5.2 overrun condition (ovr) an overrun condition occurs, when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 9.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 9.4.3.2 slave select man- agement . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 58 ). figure 58. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif =0 wcol=0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result 1 ST7MC1/st7mc2 98/294 serial peripheral interface (cont ? d) 9.4.5.4 single master and multimaster configurations there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured, using a device as the master and four device s as slaves (see figure 59 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 59. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device 1 ST7MC1/st7mc2 99/294 serial peripheral interface (cont ? d) 9.4.6 low power modes 9.4.6.1 using the spi to wake-up the device from halt mode in slave configuration, the spi is able to wake-up the device from halt mode through a spif inter- rupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode, it is recommended to per- form an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake-up the device from halt mode only if the slave select signal (external ss pin or the ssi bit in the spicsr register) is low when the device enters halt mode. so if slave se- lection is configured as external (see section 9.4.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 9.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the device is woken up by an interrupt with ? exit from halt mode ? capability. the data received is subsequently read from the spidr register when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overrun error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of trans- fer event spif spie yes yes master mode fault event modf yes no overrun error ovr yes no 1 ST7MC1/st7mc2 100/294 serial peripheral interface (cont ? d) 9.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or over- run error occurs (spif=1, modf=1 or ovr=1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 9.4.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 18 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 9.4.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 18. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 1 ST7MC1/st7mc2 101/294 serial peripheral interface (cont ? d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision status (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 58 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 9.4.5.2 ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 9.4.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie=1 in the spicr register. this bit is cleared by a software sequence (an access to the spicsr register while modf=1 followed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe=1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 9.4.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ? chip select ? by controlling the level of the ss slave select signal when the ssm bit is set. 0 : slave selected 1 : slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will initiate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 53 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 1 ST7MC1/st7mc2 102/294 serial peripheral interface (cont ? d) table 19. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spicsr reset value spif 0 wcol 0 or 0 modf 00 sod 0 ssm 0 ssi 0 1 ST7MC1/st7mc2 103/294 9.5 lin sci serial communication interface (lin master/slave) 9.5.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. the lin-dedicated features support the lin (local interconnect network) protocol for both master and slave nodes. this chapter is divided into sci mode and lin mode sections. for information on general sci communications, refer to the sci mode section. for lin applications, refer to both the sci mode and lin mode sections. 9.5.2 sci features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 500k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver overrun, noise and frame error detection six interrupt sources ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error ? parity interrupt parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 9.5.3 lin features ? lin master ? 13-bit lin synch break generation ? lin slave ? automatic header handling ? automatic baud rate re-synchronization based on recognition and measurement of the lin synch field (for lin slave nodes) ? automatic baud rate adjustment (at cpu fre- quency precision) ? 11-bit lin synch break detection capability ? lin parity check on the lin identifier field (only in reception) ? lin error management ? lin header timeout ? hot plugging support 1 ST7MC1/st7mc2 104/294 lin sci ? serial communication interface (cont ? d) 9.5.4 general description the interface is externally connected to another device by two pins: ? tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. ? rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through these pins, serial data is transmitted and received as characters comprising: ? an idle line prior to transmission or reception ? a start bit ? a data word (8 or 9 bits) least significant bit first ? a stop bit indicating that the character is com- plete. this interface uses three types of baud rate gener- ator: ? a conventional type for commonly-used baud rates. ? an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. ? a lin baud rate generator with automatic resyn- chronization. 1 ST7MC1/st7mc2 105/294 lin sci ? serial communication interface (sci mode) (cont ? d) figure 60. sci block diagram (in conventional baud rate generator mode) wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator sbk rwu re te ilie rie tcie tie scicr2 lhe 1 ST7MC1/st7mc2 106/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.5 sci mode - functional description conventional baud rate generator mode the block diagram of the serial control interface in conventional baud rate generator mode is shown in figure 60 . it uses 4 registers: ? two control registers (scicr1 and scicr2) ? a status register (scisr) ? a baud rate register (scibrr) extended prescaler mode two additional prescalers are available in extend- ed prescaler mode. they are shown in figure 62 . ? an extended prescaler receiver register (scier- pr) ? an extended prescaler transmitter register (sci- etpr) 9.5.5.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 reg- ister (see figure 61 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as a continuous logic high level for 10 (or 11) full bit times. a break character is a character with a sufficient number of low level bits to break the normal data format followed by an extra ? 1 ? bit to acknowledge the start bit. figure 61. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle line bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle line start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break character start bit extra ? 1 ? data character break character start bit extra ? 1 ? data character next data character next data character 1 ST7MC1/st7mc2 107/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.5.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) be- tween the internal bus and the transmit shift regis- ter (see figure 60 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scietpr registers. ? set the te bit to send a preamble of 10 (m=0) or 11 (m=1) consecutive ones (idle line) as first transmission. ? access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: ? the tdr register is empty. ? the data transfer is beginning. ? the next data can be written in the scidr regis- ter without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i[|1:0] bits are cleared in the ccr register. when a transmission is taking place, a write in- struction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write in- struction to the scidr register places the data di- rectly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a character transmission is complete (after the stop bit or after the break character) the tc bit is set and an interrupt is generated if the tcie is set and the i[1:0] bits are cleared in the ccr reg- ister. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit l oads the shift register with a break character. the break character length de- pends on the m bit (see figure 61 ) as long as the sbk bit is set, the sci sends break characters to the tdo pin. after clearing this bit by software, the sci inserts a logic 1 bit at the end of the last break character to guarantee the recogni- tion of the start bit of the next character. idle line setting the te bit drives the sci to send a pream- ble of 10 (m=0) or 11 (m=1) consecutive ? 1 ? s (idle line) before the first character. in this case, clearing and then setting the te bit during a transmission sends a preamble (idle line) after the current word. note that the preamble du- ration (10 or 11 consecutive ? 1 ? s depending on the m bit) does not take into account the stop bit of the previous character. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. 1 ST7MC1/st7mc2 108/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.5.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) be- tween the internal bus and the received shift regis- ter (see figure 60 ). procedure ? select the m bit to define the word length. ? select the desired baud rate using the scibrr and the scierpr registers. ? set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: ? the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. ? an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. ? the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. idle line when an idle line is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i[|1:0] bits are cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when an overrun error occurs: ? the or bit is set. ? the rdr content will not be lost. ? the shift register will be overwritten. ? an interrupt is generated if the rie bit is set and the i[|1:0] bits are cleared in the ccr register. the or bit is reset by an access to the scisr reg- ister followed by a scidr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a character: ? the nf bit is set at the rising edge of the rdrf bit. ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a scisr register read oper- ation followed by a scidr register read operation. framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read oper- ation followed by a scidr register read operation. break character ? when a break character is received, the sci handles it as a framing error. to differentiate a break character from a framing error, it is neces- sary to read the scidr. if the received value is 00h, it is a break character. otherwise it is a framing error. 1 ST7MC1/st7mc2 109/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.5.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 9.5.5.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in figure 62 . the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the scierpr or the scietpr register. note: the extended prescaler is activated by set- ting the scietpr or scierpr register to a value other than zero. the baud rates are calculated as follows: with: etpr = 1,..,255 (see scietpr register) erpr = 1,.. 255 (see scierpr register) tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu tx = 16 * etpr*(pr*tr) f cpu rx = 16 * erpr*(pr*tr) f cpu 1 ST7MC1/st7mc2 110/294 lin sci ? serial communication interface (sci mode) (cont ? d) figure 62. sci baud rate and extended prescaler block diagram transmitter receiver scietpr scierpr extended prescaler receiver rate control extended prescaler transmitter rate control extended prescaler clock clock receiver rate transmitter rate scibrr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 conventional baud rate generator extended receiver prescaler register extended transmitter prescaler register 1 ST7MC1/st7mc2 111/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.5.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non-addressed receivers. the non-addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupts are inhibited. a muted receiver may be woken up in one of the following ways: ? by idle line detection if the wake bit is reset, ? by address mark detection if the wake bit is set. idle line detection receiver wakes-up by idle line detection when the receive line has recognised an idle line. then the rwu bit is reset by hardware but the idle bit is not set. this feature is useful in a multiprocessor system when the first characters of the message deter- mine the address and when each message ends by an idle line: as soon as the line becomes idle, every receivers is waken up and analyse the first characters of the message which indicates the ad- dressed receiver. the receivers which are not ad- dressed set rwu bit to enter in mute mode. con- sequently, they will not treat the next characters constituting the next part of the message. at the end of the message, an idle line is sent by the transmitter: this wakes up every receivers which are ready to analyse the addressing characters of the new message. in such a system, the inter-characters space must be smaller than the idle time. address mark detection receiver wakes-up by address mark detection when it received a ? 1 ? as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. this feature is useful in a multiprocessor system when the most significant bit of each character (except for the break character) is reserved for ad- dress detection. as soon as the receivers re- ceived an address character (most significant bit = ? 1 ? ), the receivers are waken up. the receivers which are not addressed set rwu bit to enter in mute mode. consequently, they will not treat the next characters constituting the next part of the message. 9.5.5.7 parity control hardware byte parity control (generation of parity bit in transmission and parity checking in recep- tion) can be enabled by setting the pce bit in the scicr1 register. depending on the character for- mat defined by the m bit, the possible sci charac- ter formats are as listed in table 20 . note : in case of wake up by an address mark, the msb bit of the data is taken into account and not the parity bit table 20. character formats legend: sb = start bit, stb = stop bit, pb = parity bit even parity: the parity bit is calculated to obtain an even number of ? 1s ? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ? 1s ? inside the character made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the in- terface checks if the received data byte has an even number of ? 1s ? if even parity is selected (ps=0) or an odd number of ? 1s ? if odd parity is se- lected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is gen- erated if pcie is set in the scicr1 register. m bit pce bit character format 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data | pb | stb | 1 ST7MC1/st7mc2 112/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.6 low power modes 9.5.7 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmit- ting/receiving until halt mode is exit- ed. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission com- plete tc tcie yes no received data ready to be read rdrf rie yes no overrun error or lin synch error detected or/ lhe yes no idle line detected idle ilie yes no parity error pe pie yes no lin header detection lhdf lhie yes no 1 ST7MC1/st7mc2 113/294 lin sci ? serial communication interface (sci mode) (cont ? d) 9.5.8 sci mode register description status register (scisr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register bit 6 = tc transmission complete. this bit is set by hardware when transmission of a character containing data is complete. an inter- rupt is generated if tcie=1 in the scicr2 regis- ter. it is cleared by a software sequence (an ac- cess to the scisr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a pre- amble or a break. bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detected. this bit is set by hardware when an idle line is de- tected. an interrupt is generated if the ilie=1 in the scicr2 register. it is cleared by a software se- quence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). bit 3 = or overrun error the or bit is set by hardware when the word cur- rently being received in the shift register is ready to be transferred into the rdr register whereas rdrf is still set. an interrupt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register fol- lowed by a read to the scidr register). 0: no overrun error 1: overrun error detected note: when this bit is set, rdr register contents will not be lost but the shift register will be overwrit- ten. bit 2 = nf character noise flag this bit is set by hardware when noise is detected on a received character. it is cleared by a software sequence (an access to the scisr register fol- lowed by a read to the scidr register). 0: no noise 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error or break character detected notes: ? this bit does not generate an interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both a frame error and an overrun error, it will be transferred and only the or bit will be set. bit 0 = pe parity error. this bit is set by hardware when a byte parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the sta- tus register followed by an access to the scidr data register). an interrupt is generated if pie=1 in the scicr1 register. 0: no parity error 1: parity error detected 70 tdre tc rdrf idle or 1) nf 1) fe 1) pe 1) 1 ST7MC1/st7mc2 114/294 lin sci ? serial communication interface (sci mode) (cont ? d) control register 1 (scicr1) read/write reset value: x000 0000 (x0h) 1) this bit has a different function in lin mode, please refer to the lin mode register description. bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 5 = scid disabled for low power consumption when this bit is set the sci prescalers and outputs are stopped and the end of the current byte trans- fer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note : the m bit must not be modified during a data transfer (both transmission and reception). bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark note: if the line bit is set, the wake bit is de-ac- tivated and replaced by the lhdm bit bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control (generation and detec- tion for byte parity, detection only for lin parity). 0: parity control disabled 1: parity control enabled bit 1 = ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity bit 0 = pie parity interrupt enable. this bit enables the interrupt capability of the hard- ware parity control when a parity error is detected (pe bit set). the parity error involved can be a byte parity error (if bit pce is set and bit lpe is reset) or a lin parity error (if bit pce is set and bit lpe is set). 0: parity error interrupt disabled 1: parity error interrupt enabled 70 r8 t8 scid m wake pce 1) ps pie 1 ST7MC1/st7mc2 115/294 lin sci ? serial communication interface (sci mode) (cont ? d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) 1) this bit has a different function in lin mode, please refer to the lin mode register description. bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: in sci interrupt is generated whenever tdre=1 in the scisr register bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. bit 3 = te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled notes: ? during transmission, a ? 0 ? pulse on the te bit ( ? 0 ? followed by ? 1 ? ) sends a preamble (idle line) after the current word. ? when te is set there is a 1 bit-time delay before the transmission starts. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled in the scisr register 1: receiver is enabled and begins searching for a start bit bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode notes: ? before selecting mute mode (by setting the rwu bit) the sci must first receive a data byte, other- wise it cannot function in mute mode with wake- up by idle line detection. ? in address mark detection wake-up configura- tion (wake bit=1) the rwu bit cannot be modi- fied by software while the rdrf bit is set. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ? 1 ? and then to ? 0 ? , the transmitter will send a br eak word at the end of the current word. data register (scidr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 60 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 60 ). 70 tie tcie rie ilie te re rwu 1) sbk 1) 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 1 ST7MC1/st7mc2 116/294 lin sci ? serial communication interface (sci mode) (cont ? d) baud rate register (scibrr) read/write reset value: 0000 0000 (00h) note: when lin slave mode is disabled, the sci- brr register controls the conventional baud rate generator. bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. bit 2:0 = scr[2:0] sci receiver rate divider. these 3 bits, in conjunction with the scp[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividing factor sct2 sct1 sct0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 rr dividing factor scr2 scr1 scr0 1000 2001 4010 8011 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 1 ST7MC1/st7mc2 117/294 lin sci ? serial communication interface (sci mode) (cont ? d) extended receive prescaler division register (scierpr) read/write reset value: 0000 0000 (00h) bit 7:0 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value other than 00h is stored in this regis- ter. the clock frequency from the 16 divider (see figure 62 ) is divided by the binary factor set in the scierpr register (in the range 1 to 255). the extended baud rate generator is not active af- ter a reset. extended transmit prescaler division register (scietpr) read/write reset value:0000 0000 (00h) bit 7:0 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value other than 00h is stored in this regis- ter. the clock frequency from the 16 divider (see figure 62 ) is divided by the binary factor set in the scietpr register (in the range 1 to 255). the extended baud rate generator is not active af- ter a reset. note: in lin slave mode, the conventional and extended baud rate generators are disabled. 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 1 ST7MC1/st7mc2 118/294 lin sci ? serial communication interface (lin mode) 9.5.9 lin mode - functional description. the block diagram of the serial control interface, in lin slave mode is shown in figure 64 . it uses 6 registers: ? three control registers: scicr1, scicr2 and scicr3 ? two status registers: the scisr register and the lhlr register mapped at the scierpr address ? a baud rate register: lpr mapped at the sci- brr address and an associated fraction register lpfr mapped at the scietpr address the bits dedicated to lin are located in the scicr3. refer to the register descriptions in sec- tion 9.5.10 for the definitions of each bit. 9.5.9.1 entering lin mode to use the linsci in lin mode the following con- figuration must be set in scicr3 register: ? clear the m bit to configure 8-bit word length. ? set the line bit. master to enter master mode the lslv bit must be reset in this case, setting the sbk bit will send 13 low bits. then the baud rate can programmed using the scibrr, scierpr and scietpr registers. in lin master mode, the conventional and / or ex- tended prescaler define the baud rate (as in stand- ard sci mode) slave set the lslv bit in the scicr3 register to enter lin slave mode. in this case, setting the sbk bit will have no effect. in lin slave mode the lin baud rate generator is selected instead of the conventional or extended prescaler. the lin baud rate generator is com- mon to the transmitter and the receiver. then the baud rate can be programmed using lpr and lprf registers. note: it is mandatory to set the lin configuration first before programming lpr and lprf, because the lin configuration uses a different baud rate generator from the standard one. 9.5.9.2 lin transmission in lin mode the same procedure as in sci mode has to be applied for a lin transmission. to transmit the lin header the proceed as fol- lows: ? first set the sbk bit in the scicr2 register to start transmitting a 13-bit lin synch break ? reset the sbk bit ? load the lin synch field (0x55) in the scidr register to request synch field transmission ? wait until the scidr is empty (tdre bit set in the scisr register) ? load the lin message identifier in the scidr register to request identifier transmission. 1 ST7MC1/st7mc2 119/294 figure 63. lin characters bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle line start bit 8-bit word length (m bit is reset) lin synch break = 13 low bits start bit extra ? 1 ? data character next data character bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field lin synch field measurement for baud rate autosynchronization 1 ST7MC1/st7mc2 120/294 lin sci ? serial communication interface (lin mode) (cont ? d) figure 64. sci block diagram in lin slave mode wake up unit receiver control scisr transmit control tdre tc rdrf idle or/ nf fe pe sci control interrupt scicr1 r8 t8 scid m wake pce ps pie received data register (rdr) receive shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) scidr transmitter clock receiver clock f cpu / ldiv sbk rwu re te ilie rie tcie tie scicr2 lin slave baud rate auto synchronization f cpu scicr3 line lase lhie lsf lhdf extended prescaler conventional baud rate generator + /16 scibrr lpr7 lpr0 lin slave baud rate generator 0 1 unit ldum lhdm lhe lslv 1 ST7MC1/st7mc2 121/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.9.3 lin reception in lin mode the reception of a byte is the same as in sci mode but the linsci has features for han- dling the lin header automatically (identifier de- tection) or semiautomatically (synch break detec- tion) depending on the lin header detection mode. the detection mode is selected by the lhdm bit in the scicr3. additionally, an automatic resynchronization fea- ture can be activated to compensate for any clock deviation, for more details please refer to section 9.5.9.5 lin baudrate . lin header handling by a slave depending on the lin header detection method the linsci will signal the detection of a lin head- er after the lin synch break or after the identifier has been successfully received. note: it is recommended to combine the header detec- tion function with mute mode. putting the linsci in mute mode allows the detection of headers only and prevents the reception of any other charac- ters. this mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not rele- vant for the application. synch break detection (lhdm = 0): when a lin synch break is received: ? the rdrf bit in the scisr register is set. it in- dicates that the content of the shift register is transferred to the scidr register, a value of 0x00 is expected for a break. ? the lhdf flag in the scicr3 register indicates that a lin synch break field has been detected. ? an interrupt is generated if the lhie bit in the scicr3 register is set and the i[1:0] bits are cleared in the ccr register. ? then the lin synch field is received and meas- ured. ? if automatic resynchronization is enabled (la- se bit = 1), the lin synch field is not trans- ferred to the shift register: there is no need to clear the rdrf bit. ? if automatic resynchronization is disabled (la- se bit =0), the lin synch field is received as a normal character and transferred to the scidr register and rdrf is set. note: in lin slave mode, the fe bit detects all frame er- ror which does not correspond to a break. identifier detection (lhdm = 1): this case is the same as the previous one except that the lhdf and the rdrf flags are set only af- ter the entire header has been received (this is true whether automatic resynchronization is ena- bled or not). this indicates that the lin identifier is available in the scidr register. notes: during lin synch field measurement, the sci state machine is switched off: no characters are transferred to the data register. lin slave parity in lin slave mode (line and lslv bits are set) lin parity checking can be enabled by setting the pce bit. in this case, the parity bits of the lin identifier field are checked. the identifier character is rec- ognised as the 3 rd received character after a break character (included): the bits involved are the two msb positions (7 th and 8 th bits if m=0; 8 th and 9 th bits if m=0) of the identifier character. the check is performed as specified by the lin specification: lin synch lin synch identifier parity bits field field break identifier field parity bits id0 start bit stop bit id1 id2 id3 id4 id5 p0 p1 identifier bits p1 id1 id3 id4 id5 = p0 id0 = id1 id2 id4 m=0 1 ST7MC1/st7mc2 122/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.9.4 lin error detection lin header error flag the lin header error flag indicates that an invalid lin header has been detected. when a lin header error occurs: ? the lhe flag is set ? an interrupt is generated if the rie bit is set and the i[1:0] bits are cleared in the ccr register. if autosynchronization is enabled (lase bit =1), this can mean that the lin synch field is corrupt- ed, and that the sci is in a blocked state (lsf bit is set). the only way to recover is to reset the lsf bit and then to clear the lhe bit. ? the lhe bit is reset by an access to the scisr register followed by a read of the scidr register. lhe/ovr error conditions when auto resynchronization is disabled (lase bit =0), the lhe flag detects: ? that the received lin synch field is not equal to 55h. ? that an overrun occurred (as in standard sci mode) ? furthermore, if lhdm is set it also detects that a lin header reception timeout occurred (only if lhdm is set). when the lin auto-resynchronization is enabled (lase bit=1), the lhe flag detects: ? that the deviation error on the synch field is outside the lin specification which allows up to +/-15.5% of period deviation between the slave and master oscillators. ? a lin header reception timeout occurred. if t header > t header_max then the lhe flag is set. refer to figure 65 . (only if lhdm is set to 1) ? an overflow during the synch field measure- ment, which leads to an overflow of the divider registers. if lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). ? that an overrun occurred on fields other than the synch field (as in standard sci mode) deviation error on the synch field the deviation error is checking by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the master oscillator). two checks are performed in parallel: ? the first check is based on a measurement be- tween the first falling edge and the last falling edge of the synch field. let ? s refer to this period deviation as d: if the lhe flag is set, it means that: d > 15.625% if lhe flag is not set, it means that: d < 16.40625% if 15.625% d < 16.40625%, then the flag can be either set or reset depending on the dephas- ing between the signal on the rdi line and the cpu clock. ? the second check is based on the measurement of each bit time between both edges of the synch field: this checks that each of these bit times is large enough compared to the bit time of the cur- rent baud rate. when lhe is set due to this error then the sci goes into a blocked state (lsf bit is set). lin header time-out error when the lin identifier field detection method is used (by configuring lhdm to 1) or when lin auto-resynchronization is enabled (l ase bit=1), the linsci automatically monitors the t header_max condition given by the lin protocol. if the entire header (up to and including the stop bit of the lin identifier field) is not received within the maximum time limit of 57 bit times then a lin header error is signalled and the lhe bit is set in the scisr register. figure 65. lin header reception timeout the time-out counter is enabled at each break de- tection. it is stopped in the following conditions: - a lin identifier field has been received - an lhe error occurred (other than a timeout er- ror). - a software reset of lsf bit (transition from high to low) occurred during the analysis of the lin synch field or if lhe bit is set due to this error during the lin synchr field (if lase bit = 1) then the sci goes into a blocked state (lsf bit is set). lin synch lin synch identifier field field break t header 1 ST7MC1/st7mc2 123/294 lin sci ? serial communication interface (lin mode) (cont ? d) if lhe bit is set due to this error during fields other than lin synch field or if lase bit is reset then the current received header is discarded and the sci searches for a new break field. note on lin header time-out limit according to the lin specification, the maximum length of a lin header which does not cause a timeout is equal to 1.4*(34 + 1) = 49 t bit_master . t bit_master refers to the master baud rate. when checking this timeout, the slave node is de- synchronized for the reception of the lin break and synch fields. consequently, a margin must be allowed, taking into account the worst case: this occurs when the lin identifier lasts exactly 10 t bit_master periods. in this case, the lin break and synch fields last 49-10 = 39t bit_master peri- ods. assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. this leads to a maximum allowed header length of: 39 x (1/0.845) t bit_master + 10t bit_master = 56.15 t bit_slave a margin is provided so that the time-out occurs when the header length is greater than 57 t bit_slave periods. if it is less than or equal to 57 t bit_slave periods, then no timeout occurs. lin header length even if no timeout occurs on the lin header, it is possible to have access to the effective lin head- er length (t header ) through the lhl register. this allows monitoring at software level the t frame_max condition given by the lin protocol. this feature is only available when lhdm bit =1 or when lase bit =1. mute mode and errors in mute mode when lhdm bit =1, if an lhe error occurs during the analysis of the lin synch field or if a lin header time-out occurs then the lhe bit is set but it doesn ? t wake up from mute mode. in this case, the current header analysis is discarded. if needed, the software has to reset lsf bit. then the sci searches for a new lin header. in mute mode, if a framing error occurs on a data (which is not a break), it is discarded and the fe bit is not set. when lhdm bit =1, any lin header which re- spects the following conditions causes a wake up from mute mode: - a valid lin break field (at least 11 dominant bits followed by a recessive bit) - a valid lin synch field (without deviation error) - a lin identifier field without framing error. note that a lin parity error on the lin identifier field does not prevent wake up from mute mode. - no lin header time-out should occur during header reception. figure 66. lin synch field measurement lin synch break extra ? 1 ? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br = sm.t cpu lpr(n) lpr(n+1) lpr = t br / (16.t cpu ) = rounding (sm / 128) t cpu = cpu period t br = baud rate period t br t br = 16.lp.t cpu sm=synch measurement register (15 bits) 1 ST7MC1/st7mc2 124/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.9.5 lin baudrate baud rate programming is done by writing a value in the lpr prescaler or performing an automatic resynchronization as described below. automatic resynchronization to automatically adjust the baud rate based on measurement of the lin synch field: ? write the nominal lin prescaler value (usually depending on the nominal baud rate) in the lpfr / lpr registers. ? set the lase bit to enable the auto synchroni- zation unit. when auto synchronization is enabled, after each lin synch break, the time duration between 5 fall- ing edges on rdi is sampled on f cpu and the re- sult of this measurement is stored in an internal 15-bit register called sm (not user accessible) (see figure 66 ). then the ldiv value (and its as- sociated lpfr and lpr registers) are automati- cally updated at the end of the fifth falling edge. during lin synch field measurement, the sci state machine is stopped and no data is trans- ferred to the data register. 9.5.9.6 lin slave baud rate generation in lin mode, transmission and reception are driv- en by the lin baud rate generator note: lin master mode uses the extended or conventional prescaler register to generate the baud rate. if line bit = 1 and lslv bit = 1 then the conven- tional and extended baud rate generators are disabled: the baud rate for the receiver and trans- mitter are both set to the same value, depending on the lin slave baud rate generator: with: ldiv is an unsigned fixed point number. the man- tissa is coded on 8 bits in the lpr register and the fraction is coded on 4 bits in the lpfr register. if lase bit = 1 then ldiv is automatically updated at the end of each lin synch field. three registers are used internally to manage the auto-update of the lin divider (ldiv): - ldiv_nom (nominal value written by software at lpr/lpfr addresses) - ldiv_meas (results of the field synch meas- urement) - ldiv (used to generate the local baud rate) the control and interactions of these registers is explained in figure 67 and figure 68 . it depends on the ldum bit setting (lin divider update meth- od) note: as explained in figure 67 and figure 68 , ldiv can be updated by two concurrent actions: a transfer from ldiv_meas at the end of the lin sync field and a transfer from ldiv_nom due to a software write of lpr. if both operations occur at the same time, the transfer from ldiv_nom has priority. tx = rx = (16 * ldiv) f cpu 1 ST7MC1/st7mc2 125/294 lin sci ? serial communication interface (lin mode) (cont ? d) figure 67. ldiv read / write operations when ldum=0 figure 68. ldiv read / write operations when ldum=1 mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generarion lin sync field measurement write lpr mant(7:0) ldiv frac(3:0) ldiv_nom baud rate read lpr write lpfr update rdrf=1 at end of synch field frac(3:0) mant(7:0) ldiv_meas frac(3:0) mant(7:0) write lpr read lpfr generarion lin sync field measurement 1 ST7MC1/st7mc2 126/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.9.7 lin sci clock tolerance lin sci clock tolerance when unsynchronized when lin slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the lin sci clock is +/-15%. if the deviation is within this range then the lin synch break is detected properly when a new re- ception occurs. this is made possible by the fact that masters send 13 low bits for the lin synch break, which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a ? fast ? slave and then considered as a lin synch break. according to the lin specifica- tion, a lin synch break is valid when its duration is greater than t sbrkts = 10. this means that the lin synch break must last at least 11 low bits. note: if the period desynchronization of the slave is +15% (slave too slow), the character ? 00h ? which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35). consequently, a valid lin synch break must last at least 11 low bits. lin sci clock tolerance when synchronized when synchronization has been performed, fol- lowing reception of a lin synch break, the lin sci, in lin mode, has the same clock deviation toler- ance as in sci mode, which is explained below: during reception, each bit is oversampled 16 times. the mean of the 8 th , 9 th and 10 th samples is considered as the bit value. consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%. 9.5.9.8 clock deviation causes the causes which contribute to the total deviation are: ? d tra : deviation due to transmitter error. note: the transmitter can be either a master or a slave (in case of a slave listening to the re- sponse of another slave). ? d meas : error due to the lin synch measure- ment performed by the receiver. ? d quant : error due to the baud rate quantisa- tion of the receiver. ? d rec : deviation of the local oscillator of the receiver: this deviation can occur during the reception of one complete lin message as- suming that the deviation has been compen- sated at the beginning of the message. ? d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the lin sci clock tolerance: d tra + d meas +d quant + d rec + d tcl < 3.75% figure 69. bit sampling in reception mode rdi line sample clock 123456789101112131415 16 sampled values one bit time 6/16 7/16 7/16 1 ST7MC1/st7mc2 127/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.9.9 error due to lin synch measurement the lin synch field is measured over eight bit times. this measurement is performed using a counter clocked by the cpu clock. the edge detections are performed using the cpu clock cycle. this leads to a precision of 2 cpu clock cycles for the measurement which lasts 16*8*ldiv clock cy- cles. consequently, this error (d meas ) is equal to: 2 / (128*ldiv min ). ldiv min corresponds to the minimum lin prescal- er content, leading to the maximum baud rate, tak- ing into account the maximum deviation of +/-15%. 9.5.9.10 error due to baud rate quantisation the baud rate can be adjusted in steps of 1 / (16 * ldiv). the worst case occurs when the ? real ? baud rate is in the middle of the step. this leads to a quantization error (d quant ) equal to 1 / (2*16*ldiv min ). 9.5.9.11 impact of clock deviation on maximum baud rate the choice of the nominal baud rate (ldiv nom ) will influence both the quantisation error (d quant ) and the measurement error (d meas ). the worst case occurs for ldiv min . consequently, at a given cpu frequency, the maximum possible nominal baud rate (lpr min ) should be chosen with respect to the maximum tol- erated deviation given by the equation: d tra + 2 / (128*ldiv min ) + 1 / (2*16*ldiv min ) + d rec + d tcl < 3.75% example: a nominal baud rate of 20kbits/s at t cpu = 125ns (8mhz) leads to ldiv nom = 25d. ldiv min = 25 - 0.15*25 = 21.25 d meas = 2 / (128*ldiv min ) * 100 = 0.00073% d quant = 1 / (2*16*ldiv min ) * 100 = 0.0015% lin slave systems for lin slave systems (the line and lslv bits are set), receivers wake up by lin synch break or lin identifier detection (depending on the lhdm bit). hot plugging feature for lin slave nodes in lin slave mute mode (the line, lslv and rwu bits are set) it is possible to hot plug to a net- work during an ongoing communication flow. in this case the sci monitors the bus on the rdi line until 11 consecutive dominant bits have been de- tected and discards all the other bits received. 1 ST7MC1/st7mc2 128/294 lin sci ? serial communication interface (lin mode) (cont ? d) 9.5.10 lin mode register description status register (scisr) read only reset value: 1100 0000 (c0h) bits 7:4 = same function as in sci mode, please refer to section 9.5.8 sci mode register descrip- tion . bit 3 = lhe lin header error . during lin header this bit signals three error types: ? the lin synch field is corrupted and the sci is blocked in lin synch state (lsf bit=1). ? a timeout occurred during lin header reception ? an overrun error was detected on one of the header field (see or bit description in section 9.5.8 sci mode register description )). an interrupt is generated if rie=1 in the scicr2 register. if blocked in the lin synch state, the lsf bit must first be reset (to exit lin synch field state and then to be able to clear lhe flag). then it is cleared by the following software sequence : an access to the scisr register followed by a read to the scidr register. 0: no lin header error 1: lin header error detected note: apart from the lin header this bit signals an over- run error as in sci mode, (see description in sec- tion 9.5.8 sci mode register description ) bit 2 = nf noise flag in lin master mode (line bit = 1 and lslv bit = 0) this bit has the same function as in sci mode, please refer to section 9.5.8 sci mode register description in lin slave mode (line bit = 1 and lslv bit = 1) this bit has no meaning. bit 1 = bit 1 = fe framing error. in lin slave mode, this bit is set only when a real framing error is detected (if the stop bit is dominant (0) and at least one of the other bits is recessive (1). it is not set when a break occurs, the lhdf bit is used instead as a break flag (if the lhdm bit=0). it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error 1: framing error detected bit 0 = pe parity error. this bit is set by hardware when a lin parity error occurs (if the pce bit is set) in receiver mode. it is cleared by a software sequence (a read to the sta- tus register followed by an access to the scidr data register). an interrupt is generated if pie=1 in the scicr1 register. 0: no lin parity error 1: lin parity error detected control register 1 (scicr1) read/write reset value: x000 0000 (x0h) bits 7:3 = same function as in sci mode, please refer to section 9.5.8 sci mode register descrip- tion . bit 2 = pce parity control enable. this bit is set and cleared by software. it selects the hardware parity control for lin identifier parity check. 0: parity control disabled 1: parity control enabled when a parity error occurs, the pe bit in the scisr register is set. bit 1 = reserved bit 0 = same function as in sci mode, please refer to section 9.5.8 sci mode register description . 70 tdre tc rdrf idle lhe nf fe pe 70 r8 t8 scid m wake pce ps pie 1 ST7MC1/st7mc2 129/294 lin sci ? serial communication interface (lin mode) (cont ? d) control register 2 (scicr2) read/write reset value: 0000 0000 (00h) bits 7:2 same function as in sci mode, please re- fer to section 9.5.8 sci mode register descrip- tion . bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode notes: ? mute mode is recommended for detecting only the header and avoiding the reception of any other characters. for more details please refer to section 9.5.9.3 lin reception . ? in lin slave mode, when rdrf is set, the soft- ware can not set or clear the rwu bit. bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ? 1 ? and then to ? 0 ? , the transmitter will send a break word at the end of the current word. control register 3 (scicr3) read/write reset value: 0000 0000 (00h) bit 7= ldum lin divider update method. this bit is set and cleared by software and is also cleared by hardware (when rdrf=1). it is only used in lin slave mode. it determines how the lin divider can be updated by software. 0: ldiv is updated as soon as lpr is written (if no auto synchronization update occurs at the same time). 1: ldiv is updated at the next received character (when rdrf=1) after a write to the lpr register notes: - if no write to lpr is performed between the set- ting of ldum bit and the reception of the next character, ldiv will be updated with the old value. - after ldum has been set, it is possible to reset the ldum bit by software. in this case, ldiv can be modified by writing into lpr / lpfr registers. bit 6:5 = line, lslv lin mode enable bits. these bits configure the lin mode: the lin master configuration enables: the capability to send lin synch breaks (13 low bits) using the sbk bit in the scicr2 register. the lin slave configuration enables: ? the lin slave baud rate generator. the lin divider (ldiv) is then represented by the lpr and lpfr registers. the lpr and lpfr reg- isters are read/write accessible at the address of the scibrr register and the address of the scietpr register ? management of lin headers. ? lin synch break detection (11-bit dominant). ? lin wake-up method (see lhdm bit) instead of the normal sci wake-up method. ? inhibition of break transmission capability (sbk has no effect) ? lin parity checking (in conjunction with the pce bit) bit 4 = lase lin auto synch enable. this bit enables the auto synch unit (asu). it is set and cleared by software. it is only usable in lin slave mode. 0: auto synch unit disabled 1: auto synch unit enabled. bit 3 = lhdm lin header detection method this bit is set and cleared by software. it is only us- able in lin slave mode. it enables the header de- tection method. in addition if the rwu bit in the 70 tie tcie rie ilie te re rwu sbk 70 ldum line lslv lase lhdm lhie lhdf lsf line lslv meaning 0 x lin mode disabled 1 0 lin master mode 1 1 lin slave mode 1 ST7MC1/st7mc2 130/294 lin sci ? serial communication interface (lin mode) (cont ? d) scicr2 register is set, the lhdm bit selects the wake-up method (replacing the wake bit). 0: lin synch break detection method 1: lin identifier field detection method bit 2 = lhie lin header interrupt enable this bit is set and cleared by software. it is only us- able in lin slave mode. 0: lin header interrupt is inhibited. 1: an sci interrupt is generated whenever lhdf=1. bit 1= lhdf lin header detection flag this bit is set by hardware when a lin header is detected and cleared by a software sequence (an access to the scisr register followed by a read of the scicr3 register). it is only usable in lin slave mode. 0: no lin header detected. 1: lin header detected. notes: the header detection method depends on the lhdm bit: ? if lhdm=0, a header is detected as a lin synch break. ? if lhdm=1, a header is detected as a lin identifier, meaning that a lin synch break field + a lin synch field + a lin identifier field have been consecutively received. bit 0= lsf lin synch field state this bit indicates that the lin synch field is being analyzed. it is only used in lin slave mode. in auto synchronization mode (l ase bit=1), when the sci is in the lin synch field state it waits or counts the falling edges on the rdi line. it is set by hardware as soon as a lin synch break is detected and cleared by hardware when the lin synch field analysis is finished (see figure 70 ). this bit can also be cleared by software to exit lin synch state and return to idle mode. 0: the current character is not the lin synch field 1: lin synch field state (lin synch field under- going analysis) figure 70. lsf bit set and clear lin divider registers ldiv is coded using the two registers lpr and lp- fr. in lin slave mode, the lpr register is acces- sible at the address of the scibrr register and the lpfr register is accessible at the address of the scietpr register. lin prescaler register (lpr) read/write reset value: 0000 0000 (00h) lpr[7:0] lin prescaler (mantissa of ldiv) these 8 bits define the value of the mantissa of the lin divider (ldiv): caution: lpr and lpfr registers have different meanings when reading or writing to them. conse- quently bit manipulation instructions (bres or bset) should never be used to modify the lpr[7:0] bits, or the lpfr[3:0] bits. 70 lpr7 lpr6 lpr5 lpr4 lpr3 lpr2 lpr1 lpr0 lpr[7:0] rounded mantissa (ldiv) 00h sci clock disabled 01h 1 ... ... feh 254 ffh 255 lin synch lin synch identifier parity bits field field break 11 dominant bits lsf bit 1 ST7MC1/st7mc2 131/294 lin sci ? serial communication interface (lin mode) (cont ? d) lin prescaler fraction register (lpfr) read/write reset value: 0000 0000 (00h) bits 7:4= reserved. bits 3:0 = lpfr[3:0] fraction of ldiv these 4 bits define the fraction of the lin divider (ldiv): 1. when initializing ldiv, the lpfr register must be written first. then, the write to the lpr register will effectively update ldiv and so the clock gen- eration. 2. in lin slave mode, if the lpr[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off. examples of ldiv coding: example 1: lpr = 27d and lpfr = 12d this leads to: mantissa (ldiv) = 27d fraction (ldiv) = 12/16 = 0.75d therefore ldiv = 27.75d example 2: ldiv = 25.62d this leads to: lpfr = rounded(16*0.62d) = rounded(9.92d) = 10d = ah lpr = mantissa (25.620d) = 25d = 1bh example 3: ldiv = 25.99d this leads to: lpfr = rounded(16*0.99d) = rounded(15.84d) = 16d 70 0000 lpfr 3 lpfr 2 lpfr 1 lpfr 0 lpfr[3:0] fraction (ldiv) 0h 0 1h 1/16 ... ... eh 14/16 fh 15/16 1 ST7MC1/st7mc2 132/294 lin sci ? serial communication interface (lin mode) (cont ? d) lin header length register (lhlr) read only reset value: 0000 0000 (00h). note: in lin slave mode when l ase = 1 or lhdm = 1, the lhlr register is accessible at the address of the scierpr register. otherwise this register is always read as 00h. bit 7:0 = lhl[7:0] lin header length. this is a read-only register, which is updated by hardware if one of the following conditions occurs: - after each break detection, it is loaded with ? ffh ? . - if a timeout occurs on t header , it is loaded with 00h. - after every successful lin header reception (at the same time than the setting of lhdf bit), it is loaded with a value (lhl) which gives access to the number of bit times of the lin header length (t header ). the coding of this value is explained below: lhl coding: t header_max = 57 lhl(7:2) represents the mantissa of (57 - t head- er ) lhl(1:0) represents the fraction (57 - t header ) example of lhl coding: example 1: lhl = 33h = 001100 11b lhl(7:3) = 1100b = 12d lhl(1:0) = 11b = 3d this leads to: mantissa (57 - t header ) = 12d fraction (57 - t header ) = 3/4 = 0.75 therefore: (57 - t header ) = 12.75d and t header = 44.25d example 2: 57 - t header = 36.21d lhl(1:0) = rounded(4*0.21d) = 1d lhl(7:2) = mantissa (36.21d) = 36d = 24h therefore lhl(7:0) = 10010001 = 91h example 3: 57 - t header = 36.90d lhl(1:0) = rounded(4*0.90d) = 4d the carry must be propagated to the matissa : lhl(7:2) = mantissa (36.90d) + 1= 37d = therefore lhl(7:0) = 10110000= a0h 70 lhl7 lhl6 lhl5 lhl4 lhl3 lhl2 lhl1 lhl0 lhl[7:2] mantissa (57 - t header ) mantissa ( t header ) 0h 0 57 1h 1 56 ... ... ... 39h 56 1 3ah 57 0 3bh 58 never occurs ... ... ... 3eh 62 never occurs 3fh 63 initial value lhl[1:0] fraction (57 - t header ) 0h 0 1h 1/4 2h 1/2 3h 3/4 1 ST7MC1/st7mc2 133/294 serial communication interface (cont ? d) table 21. sci register map and reset values addr. (hex.) register name 7654 3 210 0018h sci1sr reset value tdre 1 tc 1 rdrf 0 idle 0 or/lhe 0 nf 0 fe 0 pe 0 0019h sci1dr reset value dr7 - dr6 - dr5 - dr4 - dr3 - dr2 - dr1 - dr0 - 001ah sci1brr lpr (lin slave mode) reset value scp1 lpr7 0 scp0 lpr6 0 sct2 lpr5 0 sct1 lpr4 0 sct0 lpr3 0 scr2 lpr2 0 scr1 lpr1 0 scr0 lpr0 0 001bh sci1cr1 reset value r8 x t8 0 scid 0 m 0 wake 0 pce 0 ps 0 pie 0 001ch sci1cr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 001dh sci1cr3 reset value ldum 0 line 0 lslv 0 lase 0 lhdm 0 lhie 0 lhdf 0 lsf 0 001eh sci1erpr lhlr (lin slave mode) reset value erpr7 lhl7 0 erpr6 lhl6 0 erpr5 lhl5 0 erpr4 lhl4 0 erpr3 lhl3 0 erpr2 lhl2 0 erpr1 lhl1 0 erpr0 lhl0 0 001fh sci1tpr lprf (lin slave mode) reset value etpr7 0 0 etpr6 0 0 etpr5 0 0 etpr4 0 0 etpr3 lprf3 0 etpr2 lprf2 0 etpr1 lprf1 0 etpr0 lprf0 0 1 ST7MC1/st7mc2 134/294 9.6 motor controller (mtc) 9.6.1 introduction the st7 motor controller (mtc) can be seen as a three-phase pulse width modulator multiplexed on six output channels and a back electromotive force (bemf) zero-crossing detector for sensor- less control of permanent magnet direct current (pm bldc) brushless motors. the mtc is particularly suited to driving brushless motors (either induction or permanent magnet types) and supports operating modes like: ? commutation step control with motor voltage regulation and current limitation ? commutation step control with motor current regulation, i.e. direct torque control ? position sensor or sensorless motor phase com- mutation control (six-step mode) ? bemf zero-crossing detection with high sensitiv- ity. the integrated phase voltage comparator is directly referred to the full bemf voltage without any attenuation. a bemf voltage down to 200 mv can be detected, providing high noise immunity and self-commutated operation in a large speed range. ? realtime motor winding demagnetization detec- tion for fine-tuning the phase voltage masking time to be applied before bemf monitoring. ? automatic and programmable delay between bemf zero-crossing detection and motor phase commutation. ? pwm generation for three-phase sinewave or three-channel independent pwm signals. table 22. mtc functional blocks section page input detection block 142 input pins 142 sensorless mode 145 d event detection 146 z event detection 147 demagnetization (d) event 149 z event generation (bemf zero crossing) 151 protection for zh event detection 153 position sensor mode 154 sampling block 155 commutation noise filter 158 speed sensor mode 160 tachogenerator mode 160 encoder mode 161 summary 162 delay manager 164 switched mode 165 autoswitched mode 167 debug option 168 checks and controls for simulated events 171 speed measurement mode 176 summary 181 pwm manager 181 voltage mode 181 over current handling in voltage mode 182 current mode 182 current feedback comparator 182 current feedback amplifier 184 measurement window 184 channel manager 186 mphst phase state register 187 emergency feature 187 dead time generator 190 programmable chopper 195 pwm generator block 196 main features 196 functional description 197 prescaler 197 pwm operating mode 197 repetition down-counter 201 pwm interrupt generation 201 timer re-synchronisation 202 pwm generator initialization and start-up 202 1 ST7MC1/st7mc2 135/294 motor controller (cont ? d) table 23. mtc registers 9.6.2 main features two on-chip analog comparators, one for bemf zero-crossing detection, the other for current regulation or limitation seven selectable reference voltages for the hysteresis comparator (0.2 v, 0.6 v, 1 v, 1.5 v, 2 v, 2.5 v, 3.5 v) and the possibility to select an external reference pin (mcvref). 8-bit timer (mtim) with three compare registers and two capture features, which may be used as the delay manager of a speed measurement unit measurement window generator for bemf zero-crossing detection filter option for the zero-crossing detection. auto-calibrated prescaler with 16 division steps 8x8-bit multiplier phase input multiplexer sophisticated output management: ? the six output channels can be split into two groups (high & low) ? the pwm signal can be multiplexed on high, low or both groups, alternatively or simultane- ously, for six-step motor drives ? 12-bit pwm generator with full modulation ca- pability (0 and 100% duty cycle), edge or cent- er-aligned patterns ? dedicated interrupt for pwm duty cycles up- dating and associated pwm repetition coun- ter. ? programmable deadtime insertion unit. ? programmable high frequency chopper in- sertion and high current pwm outputs for di- rect optocoupler drives. ? the output polarity is programmable channel by channel. ? a programmable bit (active low) forces the outputs in hiz, low or high state, depending on option byte 1 (refer to ? st7fmc device configuration and ordering information ? sec- tion). ? an ? emergency stop ? input pin (active low) asynchronously forces the outputs in hiz, low or high state, depending on option byte 1 (re- fer to ? st7fmc device configuration and or- dering information ? section). register description register page (rpgs bit) page mtim timer counter register 0 203 mtiml timer lsb (mode depend- ent) 0 203 mzprv capture z n-1 register 0 203 mzreg capture z n register 0 203 mcomp compare c n+1 register 0 203 mdreg demagnetization reg. 0 203 mwght a n weight register 0 204 mprsr prescaler & sampling reg. 0 204 mimr interrupt mask register 0 204 misr interrupt status register 0 205 mcra control register a 0 206 mcrb control register b 0 208 mcrc control register c 0 209 mphst phase state register 0 210 mdfr d event filter register 0 212 mcfr current feedback filter register 0 211 mref reference register 0 213 mpcr pwm control register 0 214 mrep repetition counter reg. 0 215 mcpwh compare w register high 0 215 mcpwl compare w register low 0 215 mcpvh compare v register high 0 215 mcpvl compare v register low 0 215 mcpuh compare u register high 0 216 mcpul compare u register low 0 216 mcp0h compare 0 register high 0 216 mcp0l compare 0 register low 0 216 mdtg dead time generator reg. 1 217 mpol polarity register 1 218 mpwme pwm register 1 219 mconf configuration register 1 220 mpar parity register 1 221 mzfr z event filter register 1 222 mscr sampling clock register 1 223 1 ST7MC1/st7mc2 136/294 motor controller (cont ? d) 9.6.3 application example: pm bldc motor drive this example shows a six-step command se- quence for a 3-phase permanent magnet dc brushless motor (pm bldc motor). figure 72 shows the phase steps and voltage, while table 24 shows the relevant phase configurations. to run this kind of motor efficiently, an autoswitch- ing mode has to be used, i.e. the position of the ro- tor must self-generate the powered winding com- mutation. the bemf zero crossing (z event) on the non-excited winding is used by the mtc as a rotor position sensor. the delay between this event and the commutation is computed by the mtc and the hardware commutation event c n is automatically generated after this delay. after the commutation occurs, the mtc waits until the winding is completely demagnetized by the free-wheeling diode: during this phase the winding is tied to 0v or to the hv high voltage rail and no bemf can be read. at the end of this phase a new bemf zero-crossing detection is enabled. the end of demagnetization event (d), is also de- tected by the mtc or simulated with a timer com- pare feature when no detection is possible. the mtc manages these three events always in the same order: z generates c after a delay com- puted in realtime, then waits for d in order to ena- ble the peripheral to detect another z event. the bemf zero-crossing event (z), can also be detected by the mtc or simulated with a timer compare feature when no detection is possible. the speed regulation is managed by the micro- controller, by means of an adjustable reference current level in case of current control, or by direct pwm duty-cycle adjustment in case of voltage control. 1 ST7MC1/st7mc2 137/294 motor controller (cont ? d) figure 71. chronogram of events (in autoswitched mode) . c h event z h or z s event cn processing wait for c n t z n c n t wait for d n d h event d n d s event wait for z v dd v ss p signal when sampled (output of the v ref (threshold value for voltage on phase a voltage on phase b voltage on phase c analog mux) input comparator) bemf sampling c h event z h or z s event cn processing wait for c n t z n c n t wait for d n d h event d n d s event wait for z v dd v ss p signal when sampled (output of the v ref (threshold value for voltage on phase a voltage on phase b voltage on phase c analog mux) input comparator) bemf sampling 1 ST7MC1/st7mc2 138/294 motor controller (cont ? d) figure 72. example of command sequence for 6-step mode (typical 3-phase pm bldc motor control) 0 5 2 1 4 3 a b c node step 1 2 3 4 5 6 1 2 3 c a b hv t4 t5 t0 t1 t2 t3 i 4 i 1 i 3 i 6 i 2 i 5 hv hv/2 0 hv hv/2 0 hv hv/2 0 demagnetization d 2 z 2 c 2 c 4 d 5 z 5 2 3 4 5 commutation delay wait for bemf = 0 hv hv/2 0v t note: control & sampling pwm influence is not represented on these simplified chronograms. switch 1 6 pwm off pulses (bemf induced by rotor) superimposed voltage - approx. hv/2 (pwm on) - approx. 0v (pwm off) 1 ST7MC1/st7mc2 139/294 motor controller (cont ? d) all detections of z n events are done during a short measurement window while the high side switch is turned off. for this reason the pwm signal is ap- plied on the high side switches. when the high side switch is off, the high side winding is tied to 0v by the free-wheeling diode, the low side winding voltage is also held at 0v by the low side on switch and the complete bemf voltage is present on the third winding: detection is then possible. table 24. step configuration summary for a detailed description of the mtc registers, see section 9.6.13 . 9.6.4 application example: ac induction motor drive although the command sequence is rather differ- ent between a pm bldc and an ac three-phase induction motor, the motor controller can be con- figured to generate three-phase sinusoidal voltag- es. a timer with three independent pwm channels is available for this purpose. based on each of the pwm reference signal, two complemented pwm signals with deadtime are generated on the output pins (6 in total), to drive directly an inverter with tri- ple half bridge topology. the variable voltage levels to be applied on the motor terminals come from continuously varying duty cycle, from one pwm period to the other (re- fer to figure 73 on page 140 ). the pwm counter generates a dedicated update event (u event) which: ? updates automatically the compare registers set- ting the duty cycle to avoid time critical issues and ensure glitchless pwm operation. ? generates a dedicated u interrupt in which the values for the next coming update event are loaded in compare preload registers. the shape of the output voltage (voltage, frequen- cy, sinewave, trapezoid, ...) is completely man- aged by the applicative software, in charge of computing the compare values to be loaded for a given pwm duty-cycle (refer to figure 74 ). configuration step 1 2 3 4 5 6 phase state register current direction a to b a to c b to c b to a c to a c to b high side t0 t0 t2 t2 t4 t4 low side t3 t5 t5 t1 t1 t3 oo[5:0] bits in mphst register 001001 100001 100100 000110 010010 011000 bemf input measurement done on: mcic mcib mcia mcic mcib mcia is[1:0] bits in mphst register 10 01 00 10 01 00 bemf edge back emf shape falling rising falling rising falling rising cpb bit in mcrb register (zvd bit = 0) 010101 hardware or hardware-simulated demagnetization voltage on measured point at the start of demagnetization 0v hv 0v hv 0v hv hdm-sdm bits in mcrb register 10 11 10 11 10 11 demagnetization switch pwm side selection to accelerate demagnetization low side high side low side high side low side high side driver selection to accelerate de- magnetization t3 t0 t5 t2 t1 t4 1 ST7MC1/st7mc2 140/294 motor controller (cont ? d) finally, the pwm modulated voltage generated by the power stage is smoothed by the motor induct- ance to get sinusoidal currents in the stator wind- ings. the induction motor being asynchronous, there is no need to synchronize the rotor position to the sinewave generation phase in most of the applica- tions. part of the mtc dedicated to delay computation and event sampling can thus be reconfigured to perform speed acquisition of the most common speed sensor, without the need of an additional standard timer. this speed measurement timer with clear-on-cap- ture and clock prescaler auto-setting allows to keep the cpu load to a minimum level while taking benefit of the embedded input comparator and edge detector. figure 73. complementary pwm generation for three-phase induction motor (1 phase represented) u event compare preload mcmp0 register processing mcmpu pwm generator counter pwm ref signal t0 t1 dead time insertion 1 ST7MC1/st7mc2 141/294 motor controller (cont ? d) figure 74. typical command signals of a three-phase induction motor phase a * phase b * phase c * c a b hv t4 t5 t0 t1 t2 t3 * these simplified chronograms represent the phase voltages after low-pass filtering of the pwm outputs reference signals 1% 0% 1% pwm output duty cycle pwm output pwm 51% 50% 49% period duty cycle pwm output duty cycle 99% 100% 99% 99% 99% 1 ST7MC1/st7mc2 142/294 motor controller (cont ? d) 9.6.5 functional description the mtc can be split into five main parts as shown in the simplified block diagram in figure 75 . each of these parts may be configured for different purposes: input detection block with a comparator, an input multiplexer and an incremental encoder interface, which may work as: ? a bemf zero-crossing detector ? a speed sensor interface the delay manager with an 8/16-bit timer and an 8x8 bit multiplier, which may work as a: ? 8-bit delay manager ? speed measurement unit the pwm manager, including a measurement window generator, a mode selector and a current comparator. the channel manager with the pwm multiplexer, polarity programming, deadtime insertion and high frequency chopping capability and emergency hiz configuration input. the three-phase pwm generator with 12-bit free-running counter and repetition counter. 9.6.6 input detection block this block can operate in position sensor mode, in sensorless mode or in speed sensor mode. the mode is selected via the sr bit in the mcra reg- ister and the tes[1:0] bits in mpar register (refer to table 35 for set-up information). the block dia- gram is shown in figure 76 for the position sen- sor/sensorless modes (tes[1:0] = 00) and in fig- ure 86 for the speed sensor mode (tes[1:0] = 01, 10, 11). 9.6.6.1 input pins the mcia, mcib and mcic input pins can be used as analog or as digital pins. ? in sensorless mode, the analog inputs are used to measure the bemf zero crossing and to de- tect the end of demagnetization if required. ? in sensor mode, the analog inputs are used to get the hall sensor information. ? in speed sensor mode (e.g. tachogenerator), the inputs are used as digital pins. when using an ac tachogenerator, a small external circuit may be needed to convert the incoming signal into a square wave signal which can be treated by the mtc. due to the presence of diodes, these pins can per- manently support an input current of 5ma. in sen- sorless mode, this feature enables the inputs to be connected to each motor phase through a single resistor. a multiplexer, programmed by the is[1:0] bits in the mphst register selects the input pins and connects them to the control logic in either sensor- less or tachogenerator mode. in encoder mode, it is mandatory to connect sensor digital outputs to the mcia and mcib pins. 1 ST7MC1/st7mc2 143/294 motor controller (cont ? d) figure 75. simplified mtc block diagram mcia mcib mcic bemf=0 mco5 mco4 mco3 mco2 mco1 mco0 phase timer delay = weight x zn mccfi mccref nmces delay =? capture zn commute [c] measurement window generator current voltage mode int/ext weight (i) (v) (v) (i) r 1 c (i) delay manager channel bemf zero-crossing detector pwm manager [z] (v) [z] : back emf zero-crossing event z n : time elapsed between two consecutive z events [c] : commutation event c n : time delayed after z event to generate c event (i): current mode (v): voltage mode mtim r 2 v dd manager 12-bit counter phase u phase w u, v, w phases phase u 1 phase v pwm generator input detection 12-bit three-phase mcvref oap oan mcpwmu mcpwmv mcpwmw (v) r 3 pcn bit oaz oaon bit + - cfav bit adc encoder unit tacho or speed measure unit (not represented) 1 ST7MC1/st7mc2 144/294 motor controller (cont ? d) figure 76. input stage in sensorless or sensor mode (bits tes[1:0] = 00) v ref input n sel reg vr[2:0] mcic mcia mcib a b c is[1:0] c s,h 00 01 10 + - input block input comparator block event detection dq cp zvd bit hdm n bit* to z h generation or or or or 1 2 2 1 cpb n bit* reo bit c s,h d s,h cpb n bit* v i 12-bit pwm generator signal u sampling frequency v0c1 bit sample c s,h d s,h * = preload register, changes taken into account at next c event mphst register mpol register mcra register mcrb register mpol register mcrb register reg c d s,h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes : updated/shifted on r ratio updated (+1 or -1) multiplier o verflow r +/- o c urrent mode v oltage mode i v reg n updated with reg n+1 on c 1 2 branch taken after c event branch taken after d event mcrc register mcvref pz bit mcra register 111 sample splg bit mcrc register sr bit mcra register mconf register ds[3:0] bits 2 1 dwf[3:0] mdfr register zwf[3:0] mzfr register sr bit mcra register to d h generation z event generation d event generation f scf 1 ST7MC1/st7mc2 145/294 motor controller (cont ? d) 9.6.6.2 sensorless mode this mode is used to detect bemf zero crossing and end of demagnetization events. the analog phase multiplexer connects the non- excited motor winding to an analog 100mv hyster- esis comparator referred to a selectable reference voltage. is[1:0] bits in mphst register allow to select the input which will be drive to the comparator (either mcia, b or c). be careful that the comparator is off until cke and/or dac bit are set in mcra register. the vr[2:0] bits in the mcrc register select the reference voltage from seven internal values de- pending on the noise level and the application volt- age supply. the reference voltage can also be set externally through the mcvref pin when the vr[2:0] bits are set. table 25. threshold voltage setting *typical value for v dd =5v. bemf detections are performed during the meas- urement window, when the excited windings are free-wheeling through the low side switches and diodes. at this stage the common star connection voltage is near to ground voltage (instead of v dd /2 when the excited windings are powered) and the complete bemf voltage is present on the non-ex- cited winding terminal, referred to the ground ter- minal. the zero crossing sampling frequency is then de- fined, in current mode, by the measurement win- dow generator frequency (sa[3:0] bits in the mprsr register) or, in voltage mode, by the pwm generator frequency and phase u duty cycle. during a short period after a phase commutation (c event), the winding where the back-emf will be read is no longer excited but needs a demagneti- sation phase during which the bemf cannot be read. a demagnetization current goes through the free-wheeling diodes and the winding voltage is stuck at the high voltage or to the ground terminal. for this reason an ? end of demagnetization event ? d must be detected on the winding before the de- tector can sense a bemf zero crossing. for the end-of-demagnetization detection, no spe- cial pwm configuration is needed, the comparator sensing is done at a selectable frequency (f scf ), see table 83 . so, the three events: c (commutation), d (demag- netization) and z (bemf zero crossing) must al- ways occur in this order in autoswitched mode when hard commutation is selected. the comparator output is processed by a detector that automatically recognizes the d or z event, de- pending on the cpb or zvd edge and level config- uration bits as described in table 30 . to avoid wrong detection of d and z events, a blanking window filter is implemented for spike fil- tering. in addition, by means of an event counter, software can filter several consecutive events up to a programmed limit before generating the d or z event internally. this is shown in figure 77 and figure 78 . vr2 vr1 vr0 vref voltage threshold 111 threshold voltage set by external mcvref pin 110 3.5v* 101 2.5v* 100 2v* 011 1.5v* 010 1v* 001 0.6v* 000 0.2v* 1 ST7MC1/st7mc2 146/294 motor controller (cont ? d) 9.6.6.3 d event detection in sensorless mode, the d window filter becomes active after each c event. it blanks out the d event during the time window defined by the dwf[3:0] bits in the mdfr register (see table 26 ). the reset value is 200s. this window filter becomes active after both hardware and software c events. the d event filter becomes active after the d win- dow filter. it counts the number of consecutive d events up to a limit defined by the def[3:0] bits in the mdfr register. the reset value is 1. the d bit is set when the counter limit is reached. sampling is done at a selectable frequency (f scf ), see table 83 . the d event filter is active only for a hardware d event (d h ). for a simulated (d s ) event, it is forced to 1. figure 77. d window and event filter flowchart note: times are indicated for 4 mhz f periph table 27. d event filter setting c no end of blanking window ? d event ? sampling limit=1? reset counter increment counter set the d bit counter=limit? no no yes yes no yes window filter event filter yes dwf3 dwf2 dwf1 dwf0 c to d window fil- ter in sensorless mode (sr=0) sr=1 0000 5 s no window filter after c event 0001 10 s 0010 15 s 0011 20 s 0100 25 s 0101 30 s 0110 35 s 0111 40 s 1000 60 s 1001 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s def3 def2 def1 def0 d event limit sr=1 0000 1 no d event filter 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 1 ST7MC1/st7mc2 147/294 motor controller (cont ? d) 9.6.6.4 z event detection in sensorless mode, the z window filter becomes active after each d event. it blanks out the z event during the time window defined by the zwf[3:0] bits in the mzfr register (see table 28 ). the reset value is 200s. this window filter becomes active after both hardware and software c events. the z event filter becomes active after the z win- dow filter. it counts the number of consecutive z events up to a limit defined by the zef[3:0] bits in the mzfr register. the reset value is 1. the z bit is set when the counter limit is reached. sampling is done at a selectable frequency (f scf ), see table 83 . the z event filter is active only for a hardware z event (z h ). for a simulated (z s ) event, it is forced to 1. figure 78. z window and event filter flowchart table 28. z window filter setting note: times are indicated for 4 mhz f periph table 29. z event filter setting d no end of blanking ? z event ? sampling limit=1? reset counter increment counter set the z bit counter=limit? no no yes yes no yes window filter event filter yes window zwf3 zwf2 zwf1 zwf0 d to z window fil- ter in sensorless mode (sr=0) sr=1 0000 5 s no win- dow filter after d event 0001 10 s 0010 15 s 0011 20 s 0100 25 s 0101 30 s 0110 35 s 0111 40 s 1000 60 s 1001 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s zef3 zef2 zef1 zef0 z event limit 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 1 ST7MC1/st7mc2 148/294 motor controller (cont ? d) table 30 shows the event control selected by the zvd and cpb bits. in most cases, the d and z events have opposite edge polarity, so the zvd bit is usually 0. table 30. zvd and cpb edge selection bits legend: dwf= d window filter def= d event filter zwf = z window filter zef = z event filter refer also to table 34 on page 158 . zvd bit cpb bit event generation vs input data sampled 00 01 10 11 note: the zvd bit is located in the mpol register, the cpb bit is in the mcrb register. cd h z dwf zwf zef def cd h z zwf dwf zef def cd h z zwf dwf def zef cd h z zwf dwf def zef 1 ST7MC1/st7mc2 149/294 motor controller (cont ? d) 9.6.6.5 demagnetization (d) event at the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. the voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star connection voltage plus the bemf voltage. in some cases (if the bemf voltage is positive and the free-wheeling diodes are at ground for example) this end of demagnetization can be seen as a voltage edge on the selected mcix input and it is called a hardware demagneti- zation event d h . see table 30 . the d event filter can be used to select the number of consecutive d events needed to gener- ate the d h event. if enabled by the hdm bit in the mcrb register, the current value of the mtim timer is captured in register mdreg when this event occurs in order to be able to simulate the demagnetization phase for the next steps. when enabled by the sdm bit in the mcrb regis- ter, demagnetization can also be simulated by comparing the mtim timer with the mdreg regis- ter. this kind of demagnetization is called simulat- ed demagnetization d s . if the hdm and sdm bits are both set, the first event that occurs, triggers a demagnetization event. for this to work correctly, a d s event must not precede a d h event because the latter could be detected as a z event. simulated demagnetization can also be always used if the hdm bit is reset and the sdm bit is set. this mode works as a programmable masking time between the c h and z events. to drive the motor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious z event. when an event occurs, (either d h or d s ) the di bit in the misr register is set and an interrupt request is generated if the dim bit of register mimr is set. caution 1: due to the alternate automatic capture and compare of the mtim timer with mdreg reg- ister by d h and d s events, the mdreg register should be manipulated with special care. caution 2: due to the event generation protection in the mzreg, mcomp and mdreg registers for soft event generation ( see ? built-in checks and controls for simulated events ? on page 171.), the value written in the mdreg register in soft demag- netisation mode (sdm=1) is checked by hardware after the c event. if this value is less than or equal to the mtim counter value at this moment, the software demagnetisation event is generated im- mediately and the mtim current value overwrites the value in the mdreg register to be able to re- use the right demagnetisation time for another simulated event generation. figure 79. d event generation mechanism mtim [8-bit up counter] d s mdreg [d n ] compare 8 d h d s hdm bit d = d h & hdm bit + d s & sdm bit d h sdm bit f(x) d register updated on r event sdm* bit hdm n bit* or 1 2 cpb n bit * c d s,h sample to z event detection * = preload register, changes taken into account at next c event to interrupt generator mcrb register mcrb register splg bit mcrc register sr bit mcra register d h mdfr register def[3:0] dwf[3:0] 1 ST7MC1/st7mc2 150/294 motor controller (cont ? d) table 31. demagnetisation (d) event generation (example for zvd=0) hdm bit meaning cpb bit = 1 cpb bit = 0 0 simulated mode (sdm bit =1 and hdm bit = 0) d = d s = output compare [mdreg, mtim registers] 1 hardware/simulat- ed mode (sdm bit = 1 and hdm bit = 1) d = d h + d s (hardware detection or output compare true) d = d h (hardware detection only) (*) note: this is a zoom to the additional voltage induced by the rotor (back emf) z c h 2 hv hv/2 0v d s z c h 2 hvv hv/2 0v d s undershoot due to motor parasite or first weak / null undershoot and (*) (*) sampling bemf positive d s z 5 hvv hv/2 0v c h (*) z c h 2 hv hv/2 0v z c h 2 hv hv/2 0v d s undershoot due to motor parasite or first weak / null undershoot and (*) (*) d h d s sampling bemf positive d h z 5 hv hv/2 0v c h (*) 1 ST7MC1/st7mc2 151/294 motor controller (cont ? d) 9.6.6.6 z event generation (bemf zero crossing) when both c and d events have occurred, the pwm may be switched to another group of outputs (depending on the os[2:0] bits in the mcrb regis- ter) and the real bemf zero crossing sampling can start (see figure 85 ). after z event, the pwm can also be switched to another group of outputs be- fore the next c event. a bemf voltage is present on the non-powered terminal but referred to the common star connec- tion of the motor whose voltage is equal to v dd /2. when a winding is free-wheeling (during pwm off- time) its terminal voltage changes to the other power rail voltage, this means if the pwm is ap- plied on the high side driver, free-wheeling will be done through the low side diode and the terminal will be 0v. this is used to force the common star connection to 0v in order to read the bemf referred to the ground terminal. consequently, bemf reading (i.e. comparison with a voltage close to 0v) can only be done when the pwm is applied on the high side drivers. when the bemf signal crosses the threshold voltage close to zero, it is called a hardware zero-crossing event z h . a filter can be implemented on the z h event detection (see figure 81 ). the z event filter register (mzfr) is used to select the number of consecutive z events needed to generate the z h event. alternatively, the pz bit can be used to enable protection as described in figure 81. on page 153 for this reason the mtc outputs can be split in two groups called low and high and the bemf read- ing will be done only when pwm is applied on one of these two groups. the reo bit in the mpol register is used to select the group to be used for bemf sensing (high side group). it has to be con- figured whatever the sampling mode. when enabled by the hz bit in mcrc register, the current value of the mtim timer is captured in reg- ister mzreg when this event occurs in order to be able to compute the real delay in the delay manag- er part for hardware commutation but also to be able to simulate zero-crossing events for other steps. when enabled by the sz bit set in the mcrc reg- ister, a zero-crossing event can also be simulated by comparing the mtim timer value with the mzreg register. this kind of zero-crossing event is called simulated zero-crossing z s . if both hz and sz bits are set in mcrc register, the first event that occurs, triggers a zero-crossing event. depending on the edge and level selection (zvd and cpb) bits and when pwm is applied on the correct group, a bemf zero crossing detection (ei- ther z h or z s ) sets the zi bit in the misr register and generates an interrupt if the zim bit is set in the mimr register. caution 1: due to the alternate automatic capture and compare of the mtim timer with mzreg reg- ister by z h and z s events, the mzreg register should be manipulated with special care. caution 2: due to the event generation protection in the mzreg, mcomp and mdreg registers for soft event generation, the value written in the mzreg register in simuated zero-crossing mode (sz=1) is checked by hardware after the d (either d h or d s ) event. if this value is less than or equal to the mtim counter value at this moment, the sim- ulated zero-crossing event is generated immedi- ately and the mtim current value overwrites the value in the mzreg register. see ? built-in checks and controls for simulated events ? on page 171. the z event also triggers some timer/multiplier op- erations, for more details see section 9.6.7 1 ST7MC1/st7mc2 152/294 motor controller (cont ? d) figure 80. z event generation zvd bit or or or 1 2 reo bit c s,h d s,h cpb n bit* sample mpol register mcrb register mpol register pz bit mcra register to d detection z s sz bit z = z h & hz bit+ z s & sz bit z h f(x) mtim [8-bit up counter] (msb) z s mzreg [z n ] compare 8 z h sz bit mcrc register mzfr register zwf[3:0] register updated on r event * = preload register, changes taken into account at next c event splg bit ds[3:0] bits hz bit mcrc register hz bit z h z to interrupt generator mzfr register zef[3:0] zwf[3:0] 1 ST7MC1/st7mc2 153/294 motor controller (cont ? d) 9.6.6.7 protection for z h event detection to avoid an erroneous detection of a hardware zero-crossing event, a filter can be enabled by set- ting the pz bit in the mcra register. this filter will ensure the detection of a z h event on an edge transition between d event and z h event. without this protection, z h event detection is done directly on the current sample in comparison with the expected state at the output of the phase com- parator. for example, if a falling edge transition (meaning a transition from 1 to 0 at the output of the phase comparator) is configured for z h event through the cpb bit in mcrb register, then, the state 0 is expected at the comparator output and once this state is detected, the z h event is gener- ated without any verification that the state at the comparator output of the previous sample was 1. the purpose of this protection filter is to be sure that the state of the comparator output at the sam- ple before was really the opposite of the current state which is generating the z h event. with this filter, the z h event generation is done on edge transition level comparison. this filter is not needed in sensor mode (sr=1) and for simulated zero-crossing event (z s ) gener- ation. when the pz bit is set, the z event filter zef[3:0] in the mzfr register is ignored. figure 81. protection of z h event detection. + - d cp s q q r d cp s q q r d cp s q q r v i f d rz sampling clock current sample previous sample phase comparator falling/rising edge mcrb register mpol register cpb* bit direct/filter pz mcra register bit 1 zvd bit v voltage mode i current mode rz rising edge zero-crossing fz falling edge zero-crossing c commutation event fz instantaneous edge z c fz crz 1 ST7MC1/st7mc2 154/294 motor controller (cont ? d) 9.6.6.8 position sensor mode in position sensor mode (sr=1 in mcra register), the rotor position information is given to the periph- eral by means of logical data on the three inputs mcia, mcib and mcic (hall sensors). for each step one of these three inputs is selected (is[1:0] bits in register mphst) in order to detect the z event. be careful that the phase comparator is off until cke and /or dac bits are set in mcra register. in sensor mode, demagnetization and the related features (such as the special pwm configuration, d s or d h management, programmable filter) are not available (see table 32 ) table 32. demagnetisation access in sensor mode configuration the rotor detection doesn ? t need a particular phase configuration to perform the measurement and a z event can be read from any detection window. the sampling is done at a selectable frequency (f scf ), see table 83 . this means that z event position sensoring is more precise than it is in sensorless mode. there is no minimum off time required for current control pwm in sensor mode so the minimum off time is set automatically to 0s as soon as the sr bit is set in the mcra register and a true 100% duty cycle can be set in the pwm compare u reg- ister for the pwm generation in voltage mode. in sensor mode, the zef[3:0] bits in the mzfr register are active and can be used to define the number of consecutive z samples needed to gen- erate the active event. procedure for reading sensor inputs in direct access mode : in direct access mode, the sen- sors can be read either when the clock are ena- bled or disabled (depending on cke it in mcra register). to read the sensor data the following steps have to be performed: 1. select direct access mode (dac bit in mcra register) 2. select the appropriate mcix input pin by means of the is[1:0] bits in the mphst register 3. read the comparator output (hst bit in the mref register) sr bit mcra register demagnetisation feature availabilty 1no 0 yes 1 ST7MC1/st7mc2 155/294 motor controller (cont ? d) 9.6.6.9 sampling block for a full digital solution, the phase comparator output sampling frequency is the frequency of the pwm signal applied to the switches and the sam- pling for the z event detection in sensorless mode is done at the end of the off time of this pwm sig- nal to avoid to have to re-create a virtual ground because when the pwm signal is off, the star point is at ground due to the free-wheeling diode. that ? s why, the sampling for z event detection is done by default during the off-state of the pwm signal and therefore at the pwm frequency. in current mode, this pwm signal is generated by a combination of the output of the measurement window generator (sa[3:0] bits), the output of the current comparator and a minimum off time set by the ot[3:0] bits for system stabilisation. in voltage mode, this pwm signal is generated by the 12-bit pwm generator signal in the compare u register with still a minimum off time required if the sampling is done at the end of the off time of the pwm signal for system stabilisation. the pwm signal is put off as soon as the current feedback reaches the current input limitation. this can add an off time to the one programmed with the 12- bit timer. for d event detection in sensorless mode, no spe- cific pwm configuration is needed and the sam- pling frequency (f scf, see table 83 ) is completely independent from the pwm signal. in sensor mode, the d event detection is not need- ed as the mcia, mcib and mcic pins are the dig- ital signals coming from the hall sensors so no specific pwm configuration is needed and the sampling for the z detection event is done at f scf , completely independent from the pwm sig- nal. in sensorless mode, if a virtual ground is created by the addition of an external circuit, sampling for the z event detection can be completely independ- ent from the pwm signal applied to the switches. setting the splg bit in the mcrc register allows a sampling frequency of f scf for z event detection independent from the pwm signal after getting the d (end of demagnetisation) event. this means that the sampling order is given either during the on time or the off time of the pwm signal. as soon as the splg bit is set in the mcrc register, the minimum off time needed for the pwm signal in current mode is set to 0s and a true 100% duty cycle can be set in the 12-bit pwm generator com- pare register in voltage mode. specific applications can require sampling for the z event detection only during the on time of the pwm signal. this can happen when the pwm sig- nal is applied only on the low side switches for z event detection. in this case, during the off time of the pwm signal, the phase voltage is tied to the application voltage v and no back-emf signal can be seen. during the on time of the pwm signal, the phase voltage can be compared to the neutral point voltage and the z event can be detected. therefore, it is possible to add a programmable delay before sampling (which is normally done when the pwm signal is switched on) to perform the sampling during the on time of the pwm sig- nal. this delay is set with the ds [3:0] bits in the mconf register. table 33. delay length before sampling note: times are indicated for 4 mhz f periph as soon as a delay is set in the ds[3:0] bits, the minimum off time for the pwm signal is no long- er required and it is automatically set to 0s in cur- rent mode in the internal sampling clock and a true 100% duty cycle can be set in the 12-bit pwm generator compare u register if needed. ds3 ds2 ds1 ds0 delay added to sample at ton 0000 no delay added. sample during toff 0 0 0 1 2.5 s 0010 5 s 0 0 1 1 7.5 s 0 1 0 0 10 s 0 1 0 1 12.5 s 0 1 1 0 15 s 0 1 1 1 17.5 s 1 0 0 0 20 s 1 0 0 1 22.5 s 1 0 1 0 25 s 1 0 1 1 27.5 s 1 1 0 0 30 s 1 1 0 1 32.5 s 1 1 1 0 35 s 1 1 1 1 37.5 s 1 ST7MC1/st7mc2 156/294 motor controller (cont ? d) depending on the frequency and the duty cycle of the pwm signal, the delay inserted before sam- pling could cause it sample the signal off time in- stead of the on time. in this case an interrupt can be generated and the sample will not be taken into acount. when a sample occurs outside the pwm signal on time, the soi bit in the mconf register is set and an interrupt request is generated if the som bit is set in the mconf register. this inter- rupt is enabled only if a delay value has been set in the ds[3:0] bits. in this case, the sampling is done at the pwm frequency but only during the on time of the pwm signal. figure 82 and figure 83 shows in detail the generation of the sampling order when the delay is added. for complete flexibility, the possibility of sampling at 1 mhz frequency during the on time of the pwm signal is also available when the splg bit is set as if there is a delay value in the ds[3:0] bits. this means that when the sampling is to be per- formed, after the delay a 1 mhz sampling window is opened until the next off time of the pwm sig- nal. the sampling out interrupt will be generated if the delay added is longer than the duty cycle of the pwm signal. as the splg bit is set and a value has been put in the ds[3:0] bits, no minimum off time is required for the pwm signal and it is auto- matically set to 0s in current mode. a true 100% duty cycle can be also set in the 12-bit timer in voltage mode. figure 84 shows in detail the sam- pling at 1 mhz during on time. figure 82. adding the delay to sample during on time for z detection figure 83. sampling out interrupt generation pwm off time current sample ds[3:0] new sample t sampling pwm signal ds[3:0] pwm off time current sample ds[3:0] t sampling pwm signal new sample during next off time. sample not taken into account. so interrupt generated. so so to interrupt generator 1 ST7MC1/st7mc2 157/294 motor controller (cont ? d) in conclusion, there are 4 sampling types that are available for z event detection in sensorless mode. 1. sampling at the end of the off time of the pwm signal at the pwm frequency 2. sampling, at a programmable frequency inde- pendent of the pwm state (either during on time or off time of the signal). sampling is done at f scf , see table 83 . 3. sampling during the on time of the pwm sig- nal by adding a delay at pwm frequency 4. sampling, at a programmable frequency during the on time (addition of a programmable delay) of the pwm signal. sampling is done at f scf , see table 83 . note 1: the sampling type is applied only for z event detection after the d event has occured. whatever the sampling type for z event detection, the sampling of the signal for d event detection is always done at the selected f scf frequency (see table 83 ), independently of the pwm signal (ei- ther during on or off time). table 34 explains the different sampling types in sensorless and in sen- sor mode. note 2: when the moe bit in the mcra register is reset (mcox outputs in reset state), and the sr bit in the mcra register is reset (sensorless mode) and the splg bit in the mcrc register is reset (sampling at pwm frequency) then, depending on the state of the zsv bit in the mscr register, z event sampling can run or be stopped (and d event is sampled). note 3: when bemf sampling is performed at the end of the pwm signal off-time, the inputs in off- state are grounded or put in hiz as selected by the diss bit in the mscr register. note 4: the zef[3:0] event counter in the mzfr register is active in all configurations. figure 84. sampling during on time at f scf pwm off state current sample f scf pwm signal ds[3:0] ds[3:0] during on time 1 ST7MC1/st7mc2 158/294 motor controller (cont ? d) 9.6.6.10 commutation noise filter for d event detection and for z event detection (when splg bit is set while ds[3:0] bits are reset), sampling is done at f scf either during the pwm on or off time ( ? sampling block ? on page 155). to avoid any erroneous detection due to pwm commutation noise, an hardware filter of 1s (for f periph = 4mhz) when pwm is put on and when pwm is put off has been implemented. this means that, with sampling at 1mhz (1s), due to this filter, 1 sample are ignored directly after the commutation. this filter is active all the time for the d event and it is active for the z event when the splg bit is set and ds[3:0] bits are cleared (meaning that the z event is sampled at high frequency either during the pwm on or off time). table 34. sensor/sensorless mode and d & z event selection note: for f scf selection, see table 83 sr bit splg bit ds[3:0] bits mode os[2:0] bits use event detection sampling clock sampling behaviour for z event detection window and event filters behaviour of the output pwm 0 0 000 sensors not used enabled d: f scf z: sa&ot config. pwm frequency at the end of the off time of the pwm sig- nal d window filter dwf[3:0] after c event d event filter def[3:0] after dwf z window filter zwf[3:0] after d event z event filter zef[3:0] after zwf see table 30 on page 148 ? before d ? behaviour, ? between d and z ? be- haviour and ? after z ? behaviour 0 1 000 sensors not used enabled d: f scf z: f scf either during off time or on time of the pwm signal ? before d ? behaviour, ? between d and z ? be- haviour and ? after z ? behaviour 00 not equal to 000 sensors not used enabled d: f scf z: sa&ot config. pwm frequency during on time of the pwm signal ? before d ? behaviour, ? between d and z ? be- haviour and ? after z ? behaviour 01 not equal to 000 sensors not used enabled d: f scf z: f scf during on time of the pwm signal ? before d ? behaviour, ? between d and z ? be- haviour and ? after z ? behaviour 1 x xxx position sensors used os1 dis- abled z: f scf either during off time or on time of the pwm signal no filter in sensor mode ? before z ? behaviour and ? after z ? behaviour 1 ST7MC1/st7mc2 159/294 motor controller (cont ? d) figure 85. functional diagram of z detection after d event begin end d s or d h change the side according to os[2:0] switch sampling clock[d] -> sampling clock[z] wait for next sampling clock edge yes no yes no yes no filter off ? read enabled z window filter turned on zwf[3:0] bits in mzfr register read enable by reo ? side change on output pwm ? 1 ST7MC1/st7mc2 160/294 motor controller (cont ? d) 9.6.6.11 speed sensor mode this mode is entered whenever the tacho edge selection bits in the mpar register are not both re- set (tes[1:0] = 10, 01, 11). the corresponding block diagram is shown in figure 86 . either incremental encoder or tachogenerator- type speed sensor can be selected with the is[1:0] bits in the mphst register. 9.6.6.12 tachogenerator mode (is[1:0] = 00, 01 or 10) any of the mcix input pins can be used as a tacho- generator input, with a digital signal (externally amplified for instance); the two remaining pins can be used as standard i/o ports. a digital multiplexer connects the chosen mcix in- put to an edge detection block. input selection is done with the is[1:0] bits in the mphst register. an edge selection block is used to select one of three ways to trigger capture events: rising edge, falling edge or both rising and falling edge sensi- tive; set-up is done with the tes[1:0] bits (keeping in mind that tes[1:0] = 00 configuration is re- served for position sensor / sensorless modes). having only one edge selected eliminates any in- coming signal dissymmetry, which may due to pole-to-pole magnet dissymmetry or from a com- parator threshold with low level signals. figure 87 presents the signals generated internal- ly with different tacho input and tes bit settings. note on hall sensors: this configuration is also suitable for motors using 3 hall sensors for position detection and not driven in six-step mode (refer to ? speed measurement mode ? on page 176). note on initializing the input stage: as the is[1:0] bits in the mphst register are preload bits (new values taken into account at c event), the in- itialization value of the is[1:0] bits has to be en- tered in direct access mode. this is done by set- ting the dac bit in the mcra register during the speed sensor input initialization routine. figure 86. input stage in speed sensor mode (tes[1:0] bits = 01, 10, 11) input n sel mcic mcia mcib 00 01 10 input block input comparator block event detection mphst register in1 clk encoder encoder interface incremental direction in2 tacho or encoder d or or edir bit clock tacho capture tes[1:0] mpar register mcrc register tacho or encoder tacho or free i/o = according to is[1:0] bits setting is[1:0] 1 ST7MC1/st7mc2 161/294 motor controller (cont ? d) 9.6.6.13 encoder mode (is[1:0] = 11) figure 88 shows the signals delivered by a stand- ard digital incremental encoder and associated in- formation: ? two 90 phased square signals with variable frequency proportional to the speed; they must be connected to mcia and mcib input pins, ? clock derived from incoming signal edges, ? direction information determined by the rela- tive phase shift of input signals ( + or -90 ). the incremental encoder interface block aims at extracting these signals. as input logic is both ris- ing and falling edge sensitive (independently from tes[1:0] bits setting), resulting clock frequency is four times the one of the input signals, thus in- creasing resolution for measurements. it may be noticed that direction bit (edir bit in mcrc register) is read only and that it does ? nt af- fect counting direction of clocked timer (cf section ). as a result, one cannot extract position informa- tion from encoder inputs during speed reversal. figure 87. tacho capture events configured by the tes[1:0] bits figure 88. incremental encoder output signals and derived information tacho input tacho capture tes[1:0]=11 tes[1:0]=01 tes[1:0]=10 mcia mcib encoder inputs encoder direction clock sampling of mcia to determine direction (edir bit) 1 ST7MC1/st7mc2 162/294 motor controller (cont ? d) note if only one encoder output is available, it may be input either on mcia or mcib and an encoder clock signal will still be generated (in this case the frequency will be 50% less than with two inputs. the state of edir bit will depend on signals present on mcia and mcib pins, the result will be given by the sampling of mcia with mcib falling edges. 9.6.6.14 summary input detection block set-up for the different avail- able modes is summarized in the table 35 . table 35. input detection block set-up input detection block mode sensor type edge sensitivity sr bit tes[1:0] bits (tacho edge selection) is[1:0] bits (input selection) position sensor hall, optical,... both rising and falling edges 1 00 00 01 10 sensorless n/a n/a 0 00 00 01 10 speed sensor incremental encoder both rising and falling edges (imposed) x any configuration dif- ferent from 00: 01 10 11 11 tachogenerator, hall, optical... rising edge 01 00 01 10 falling edge 10 00 01 10 both rising and falling edges 11 00 01 10 1 ST7MC1/st7mc2 163/294 motor controller (cont ? d) note on using the 3 mcix pins as standard i/os : when none of the mcix pins are needed in the application (for instance when driving an in- duction motor in open loop), they can be used as standard i/o ports, by configuring the motor con- troller as follows: pcn=1, tes 0 and is=11. this disables the mcix alternate functions and switch- es off the phase comparator. the state of the mcix pins is summarized in table 36 . table 36. mcix pin configuration summary *when pcn=0, tes=0 sr=0, inputs in off-state are put in hiz or grounded depending on the value of the diss bit in the mscr register. pcn tes sr is[1:0] mcia mcib mcic input detection block mode comments 0 00 0 00 analog input hi-z or gnd hi-z or gnd sensorless all mcix pins are reserved for the mtc peripheral 01 hi-z or gnd analog input hi-z or gnd 10 hi-z or gnd hi-z or gnd analog input 11 na na na na 1 00 digital input standard i/o standard i/o position sensor from 1 to 3 mcix pins reserved depending on sensor 01 standard i/o digital input standard i/o 10 standard i/o standard i/o digital input 11 na na na na 0 x xx na na na na 1 00 x 00 analog input standard i/o standard i/o na phase comparator is on. the is[1:0] bits must not be modified to avoid spurious event detection in motor controller 01 standard i/o analog input standard i/o 10 standard i/o standard i/o analog input 11 standard i/o standard i/o standard i/o na all mcix pins are standard i/os. recommended configuration: phase comparator off 00 x 00 digital input standard i/o standard i/o speed sensor tachogenerator 01 standard i/o digital input standard i/o 10 standard i/o standard i/o digital input 11 digital input digital input standard i/o speed sensor encoder 1 ST7MC1/st7mc2 164/294 motor controller (cont ? d) 9.6.7 delay manager figure 89. overview of mtim timer in switched and autoswitched mode this part of the mtc contains all the time-related functions, its architecture is based on an 8-bit shift left/shift right timer shown in figure 89 . the mtim timer includes: ? an auto-updated prescaler ? a capture/compare register for simulated de- magnetization simulation (mdreg) ? two cascaded capture and one compare regis- ters (mzreg and mzprv) for storing the times between two consecutive bemf zero crossings (z h events) and for zero-crossing event simula- tion (z s ) ? an 8x8 bit multiplier for auto computing the next commutation time ? one compare register for phase commutation generation (mcomp) the mtim timer module can work in two main modes when driving synchronous motors in six- steps mode. in switched mode the user must process the step duration and commutation time by software. in autoswitched mode the commutation action is performed automatically depending on the rotor position information and register contents. this is called the hardware commutation event c h . when enabled by the sc bit in the mcrc register, com- mutation can also be simulated by writing a value directly in the mcomp register that is compared with the mtim value. this is called simulated com- mutation c s (see ? built-in checks and controls for simulated events ? on page 171.). both in switched mode and autoswitched mode , if the sc bit in the mcrc register is set (software commutation enabled), no comparison between 8-bit up counter mtim mzreg [z n ] d s mdreg [d n ] compare z h d h ck c h,s d s,h z h,s 8 t ratio sdm* bit z clr 1 0 c swa bit = register updated on r event to interrupt generator to interrupt generator to interrupt generator mcra register mcrb register compare z s sz bit mcrc register z h / z s mzprv [z n-1 ] filter /d mzfr register zwf[3:0] filter /c mdfr register dwf[3:0] c h / c s compare mcomp [c n+1 ] sc bit mcrc register 1 ST7MC1/st7mc2 165/294 motor controller (cont ? d) the mcomp and mtim register is enabled before a write access in the mcomp register. this means that if the sc bit is set and no write access is done after in the mcomp register, no c s commutation event will occur. in speed measurement mode, when using encod- er or tachogenerator speed sensors (i.e. both tes[1:0] bits in the mpar register are not reset and the input detection block is set-up to process sensor signals), motor speed can be measured but it is not possible drive a motor in six-step mode, either sensored or sensorless. speed measurement mode is useful for motors supplied with 3-phase sinewave-modulated pwm signals: ? ac induction motors, ? permanent magnet ac (pmac) motors (al- though it needs three position sensors, they can be handled just like tachogenerator sig- nals). this mode uses only part of the delay manager ? s resources. for more details refer to ? speed meas- urement mode ? on page 176. table 37. switched and autoswitched modes 9.6.7.1 switched mode this feature allows the motor to be run step-by- step. this is useful when the rotor speed is still too low to generate a bemf. it can also run other kinds of motor without bemf generation such as induction motors or switch reluctance motors. this mode can also be used for autoswitching with all computation for the next commutation time done by software (hardware multiplier not used) and us- ing the powerful interrupt set of the peripheral. in this mode, the step time is directly written by software in the commutation compare register mcomp. when the mtim timer reaches this value a commutation occurs (c event) and the mtim timer is reset. at this time all registers with a preload function are loaded (registers marked with (*) in section 9.6.13 ). the ci bit of misr is set and if the cim bit in the misr register is set an interrupt is generat- ed. the mtim timer prescaler (step ratio bits st[3:0] in the mprsr register) is user programmable. ac- cess to this register is not allowed while the mtim timer is running (access is possible only before the starting the timer by means of the cke bit) but the prescaler contents can be incremented/decre- mented at the next commutation event by setting the rmi (decrement) or rpi (increment) bits in the misr register. when this method is used, at the next commutation event the prescaler value will be updated but also all the mtim timer-related regis- ters will be shifted in the appropriate direction to keep their value. after it has been taken into ac- count, (at commutation) the rpi or rmi bit is reset by hardware. see table 38 . only one update per step is allowed, so if both rpi and rmi bits are set together by software, this does not affect the misr register: the write access to these two bits together is not taken into account and the previous state is kept. this means that if either rpi or rmi bit was set before the write ac- cess of both bits at the same time, this bit (rpi or rmi) is kept at 1. if none of them was set before the simultaneous write access, none of them will be set after the write access. in switched mode, bemf and demagnetization de- tection are already possible in order to pass in au- toswitched mode as soon as possible but z and d events do not affect the timer contents. in this mode, if an mtim overflow occurs, it re- starts counting from 0x00h and the oi overflow flag in the mcrc register is set if the tes[1:0] bits = 00. caution : in this mode, mcomp must never be written to 0. table 38. step update swa bit commutation type mcomp user access 0 switched mode read/write 1 autoswitched mode read/write mode tes[1:0] cke bit swa bit clock state read ratio increment (slow down) ratio decrement (speed-up) x xx 0 x disabled always possible write the st[3:0] value directly in the mprsr register switched 00 1 0 enabled set rpi bit in the misr reg- ister till next commutation set rmi bit in the misr reg- ister till next commutation autoswitched 00 1 1 enabled automatically updated according to mzreg value speed measure 01 10 11 1 x enabled 1 ST7MC1/st7mc2 166/294 motor controller (cont ? d) figure 90. step ratio functional diagram f periph st[3:0] bits 4 1 / 2ratio 1 / 2 zn < 55h? mtim timer = 100h? +1 -1 ck tratio r+ r- 2 mhz - 62.5 hz ratio > 0? ratio = ratio - 1 mzreg = mzreg x 2 mzprv = mzprv x 2 mdreg = mdreg x 2 counter = counter x 2 begin end yes no z capture with mtim timer underflow (zn < 55h) ratio < fh? ratio = ratio + 1 mzreg = mzreg / 2 mzprv = mzprv/2 mdreg = mdreg/2 counter = counter/2 begin end yes no mtim timer overflow mtim timer control over t ratio and register operation slow-down control speed-up control compute mcomp mprsr register mcomp = mcomp/2** ** only in auto-switched mode (swa=1 in mcra register) 1 ST7MC1/st7mc2 167/294 motor controller (cont ? d) 9.6.7.2 autoswitched mode in this mode, using the hardware commutation event c h (sc bit reset in mcrc register), the mcomp register content is automatically comput- ed in real time as described below and in figure 91 . the c (either c s or c h ) event has no effect on the contents of the mtim timer. when a z h event occurs the mtim timer value is captured in the mzreg register, the previous cap- tured value is shifted into the mzprv register and the mtim timer is reset. see figure 71 . when a z s event occurs, the value written in the mzreg register is shifted into the mzprv register and the mtim timer is reset. one of these two registers, (when the sc bit = 0 in the mcrc register and depending on the dcb bit in the mcra register), is multiplied with the con- tents of the mwght register and divided by 256. the result is loaded in the mcomp compare reg- ister, which automatically triggers the next hard- ware commutation (c h event). note: the result of the 8*8 bit multiplication, once written in the mcomp register is compared with the current mtim value to check that the mcomp value is not already less than the mtim value due to the multiplication time. if mcomp<=mtim, a c h event is generated immediately and the mcomp value is overwritten by the mtim value. table 39. multiplier result after each shift operation the multiply is recomput- ed for greater precision. using either the mzreg or mzprv register de- pends on the motor symmetry and type. the mwght register gives directly the phase shift between the motor driven voltage and the bemf. this parameter generally depends on the motor and on the speed. setting the sc bit in the mcrc register enables the simulated commutation event (c s ) generation. this means that a write access is possible to the mcomp register and the mtim value will be com- pared directly with the value written by software in the mcomp register to generate the c s event. the comparison is enabled as soon as a write ac- cess is done to the mcomp register. this means that if the sc bit is set and no write access is done to the mcomp register, the c event will never oc- cur because no comparison will be done between mcomp and mtim. therefore, it is recommended in autoswitched mode, when using software com- mutation feature (sc bit is set) and for a normal event sequence, the corresponding value to be put in mcomp has to be written during the z inter- rupt routine (because mtim has just been reset), so that there is no spurious comparison. if the sc bit is set during a z event interrupt, then , the result of the 8*8 bits hardware multiplication can be over- written by software in the mcomp register. when simulated commutation mode is enabled, the event sequence is no longer respected, meaning that the peripheral will accept consecutive commu- tation events and not necessarily wait for a d event after a c s event. in this case the mcomp register can be written immediately after the previ- ous c event, in the c interrupt service routine for example. figure 91. c h processor block note 1 : an overflow of the mtim timer generates an rpi interrupt if the rim bit is set. note 2 : when simulated commutation mode is en- abled, the d and z event are not ignored by the peripheral, this means that if a z event happens, the mtim 8 bit internal counter will be reset. caution : mcomp must never be written to 0 for a c s event generation. dcb bit commutation delay 0 mcomp = mwght x mzprv / 256 1 mcomp = mwght x mzreg / 256 mwght [a n+1 ] mzreg [z n ] a x b / 256 mzprv [z n-1 ] dcb bit swa bit =1 & mcomp [c n+1 ] z h /z s 8 8 8 n n-1 = register updated on r event mcra register mcra register sc bit =0 mcrc register 1 ST7MC1/st7mc2 168/294 motor controller (cont ? d) auto-updated step ratio register: a) in switched mode: the mtim timer is driven by software only and any prescaler change has to be done by software (see page 165 for more details). b) in autoswitched mode: an auto-updated pres- caler always configures the mtim timer for best accuracy. figure 90 shows the process of updat- ing the step ratio bits: ? when the mtim timer value reaches ffh, the prescaler is automatically incremented in order to slow down the mtim timer and avoid an over- flow. to keep consistent values, the mtim regis- ter and all the relevant registers are shifted right (divided by two). the rpi bit in the misr register is set and an interrupt is generated (if rim is set). the timer restarts counting from its median value 0x80h and if the tes[1:0] bits = 00, the oi bit in the mcrc register is set. ? when a z-event occurs, if the mtim timer value is below 55h, the prescaler is automatically dec- remented in order to speed up the mtim timer and keep precision better than 1.2%. the mtim register and all the relevant registers are shifted left (multiplied by two). the rmi bit in the misr register is set and an interrupt is generated if rim is set. ? if the prescaler contents reach the value 0, it can no longer be automatically decremented, the mtc continues working with the same prescaler value, i.e. with a lower accuracy. no rmi in- terrrupt can be generated. ? if the prescaler contents reach the value 15, it can no longer be automatically incremented. when the timer reaches the value ffh, the pres- caler and all the relevant registers remain un- changed and no interrupt is generated, the timer restarts counting from 0x00h and if the tes[1:0] bits = 00, the oi bit in the mcrc register is set at each overflow (it has to be reset by software). the rpi bit is no longer set. the pwm is still gen- erated and the d and z detection circuitry still work, enabling the capture of the maximum timer value. the automatically updated registers are: mtim, mzreg, mzprv, mcomp and mdreg. access to these registers is summarized in table 41 . 9.6.7.3 debug option in both switched mode and autoswitched mode, setting the bit dg in mpwme register enables the debug option. this option consists of outputting the c, d and z signals in real time on pins mczem and mcdem. this is very useful during the debug phase of the application. figure 92 shows the sig- nals output on pins mcdem and mczem with the debug option. note 1: when the delay coefficient equals 0/256 (c event immediately after z event), a glitch ap- pears on mczem pin to be able to see the event even in this case. this option is also available in speed measure- ment mode with different signal outputs (see fig- ure 92 ): ? mcdem toggles when a capture event is gener- ated, ? mczem toggles every time a u event is gener- ated. these signals are only available if the tes[1:0] bits = 10, 01 or 11. note 2: in sensor mode, the mcdem output pin toggles at each c event. the mczem pin outputs the z event. 1 ST7MC1/st7mc2 169/294 motor controller (cont ? d) figure 92. output on pins mcdem and mczem with debug option (dg bit=1) c c c c d z d z d z mcdem mczem u events mcdem mczem cccccc ccc c debug outputs in speed measurement mode (tes[1:0] bits equal to 00, 01, 10). debug outputs in sensorless mode ccc c zz z mcdem mczem debug outputs in sensor mode c z z 1 ST7MC1/st7mc2 170/294 motor controller (cont ? d) note on using the auto-updated mtim timer: the auto-updated mtim timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or demagnetiza- tion. for example if an overflow occurs when calculat- ing a simulated end of demagnetization (mcomp+demagnetisation_time>ffh), the value that is stored in mdreg will be: 80h+(mcomp+demagnetization_time-ffh)/2. note on commutation interrupts: it is good prac- tice to modify the configuration for the next step as soon as possible, i.e within the commutation inter- rupt routine. all registers that need to be changed at each step have a preload register that enables the modifica- tions for a complete new configuration to be per- formed at the same time (at c event in normal mode or when writing the mphst register in direct access mode). these configuration bits are: cpb, hdm, sdm and os2 in the mcrb register and is[1:0], oo[5:0] in the mphst register. note on initializing the mtc: as shown in table 41 all the mtim timer registers are in read-write mode until the mtc clock is enabled (with the cke bit). this allows the timer, prescaler and compare reg- isters to be properly initialized for start-up. in sensorless mode, the motor has to be started in switched mode until a bemf voltage is present on the inputs. this means the prescaler st[3:0] bits and mcomp register have to be modified by soft- ware. when running the st[3:0] bits can only be incremented / decremented, so the initial value is very important. when starting directly in autoswitched mode (in sensor mode for example), write an appropriate value in the mzreg and mzprv register to per- form a step calculation as soon as the clock is en- abled. 1 ST7MC1/st7mc2 171/294 motor controller (cont ? d) 9.6.7.4 built-in checks and controls for simulated events as described in figure 89. on page 164 , mzreg, mdreg and mcomp registers are capture/com- pare registers. the compare registers are write accessible and can be used to generate simulated events. the value of the mtim timer is compared with the value written in the registers and when the mtim value reaches the corresponding register value, the simulated event is generated. simulated event generation is enabled when the correspond- ing bits are set: ? in the mcrb register for simulated demagneti- sation ? sdm for simulated demagnetisation ? in the mcrc register for simulated zero-crossing and commutation. ? sc for simulated commutation ? sz for simulated zero-crossing event. to avoid a system stop, special attention is need- ed when writing in the register to generate the cor- responding simulated event. the value written in the register has to be greater than the current val- ue of the mtim timer when writing in the registers. if the value written in the registers (mdreg, mzreg or mcomp) is already less than the cur- rent value of mtim, the simulated event will never be generated and the system will be stopped. for this reason, built-in checks and controls have been implemented in the mtim timer. if the value written in one of those registers in sim- ulated event generation mode is less than or equal to the current value of the timer when it is com- pared, the simulated event is generated immedi- ately and the value of the mtim timer at the time the simulated event occurs overwrites the value in the registers. like that the value in the register re- ally corresponds to the simulated event generation and can be re-used to generate the next simulated event. so, the value written in the registers able to gener- ate simulated events is checked by hardware and compare to the current mtim value to verify that it is greater. figure 93. simulated demagnetisation / zero-crossing event generation (sc=0) c h c h c h z h d s during c interrupt simulated or hardware d/z events value written in mdreg/mzreg if simulated event generation d h z h d s z s z s after c interrupt mdreg value checked if mdreg<=mtim immediate d s generation after d interrupt mzreg value checked if mzreg<=mtim immediate z s generation z s simulated zero-crossing d s simulated demagnetisation z h hardware zero-crossing c h hardware commutation mtim timer value t 1 ST7MC1/st7mc2 172/294 motor controller (cont ? d) when using hardware commutation c h , the se- quence of events needed is c h then d and finally z events and the value written in the registers are checked at different times. if sdm bit is set, meaning simulated demagnetisa- tion, a value must be written in the mdreg regis- ter to generate the simulated demagnetisation. this value must be written after the c (either c s or c h ) event preceding the simulated demagnetisa- tion. if sz bit is set, meaning simulated zero-crossing event, a value must be written in the mzreg reg- ister to generate the simulated zero-crossing. this value must be written after the d event (d h or d s ) preceding the simulated zero-crossing. when using simulated commutation (c s ), the re- sult of the 8*8 hardware multiplication of the delay manager is not taken in account and must be over- written if the sc bit has been set in a z event inter- rupt and the sequence of events is broken mean- ing that several consecutive simulated commuta- tions can be implemented. as soon as the sc bit is set in the mcrc register, the system won ? t necessarily expect a d event af- ter a c event. this can be used for an application in sensor mode with only one hall effect sensor for example. be careful that the d and z events are not ignored by the peripheral, this means that for example if a z event occurs, the mtim timer is reset. in simu- lated commutation mode, the sequence d -> z is expected, and this order must be repected. as the sequence of events may not be the same when using simulated commutation, as soon as the sc bit is set, the capture/compare feature and protection on mcomp register is reestablished only after a write to the mcomp register. this means that as soon as the sc bit is set, if no write access is done to the mcomp register, no com- mutation event will be generated, whatever the value of mcomp compared to mtim at the time sc is set. this does not depend on the running mode: switched or autoswitched mode (swa bit). if software commutation event is used with a nor- mal sequence of events c-->d-->z, it is recom- mended to write the mcomp register during the z interrupt routine to avoid any spurious comparison as several consecutive c s events can be generat- ed. note that two different simulated events can be used in the same step (like d s followed by z s ). note also that for more precision, it is recommend- ed to use the value captured from the preceding hardware event to compute the value used to gen- erate simulated events. figure 93 , figure 94 and figure 95 shows details of simulated event generation. 1 ST7MC1/st7mc2 173/294 motor controller (cont ? d) figure 94. simulated commutation event generation with only 1 hall effect sensor (sc bit =1) note: if the sc bit is set during z event interrupt, then the 8*8 bit hardware multiplication result can be overwritten in the mcomp register. otherwise, when the sc bit is set, the result of the multiplica- tion is not taken into account after a z event. figure 95. simulated commutation and z event c h c h z c s z z c s d c interrupt sc set in mcrc after c interrupt mcomp is written for c s event if mcomp<=mtim immediate c s generation c s c s d c interrupt sc reset in mcrb next c event = c h with 8*8 bit multiplication z zero-crossing event d demagnetisation event c h hardware commutation c s simulated commutation mtim timer value t c s c h z z z d sc bit is reset d z zero-crossing event d demagnetisation event c h hardware commutation c s simulated commutation mcomp register the result of the hardware multiplication is put in mcomp-->c h and compared sc bit is set during z it the hardware multiplication is taken into account but the value in mcomp can be overwritten c s z d sc bit is already set when z it occurs. the hardware multipli- -cation is not taken into account a value has to be written in the mcomp register mtim timer value t with mtim once written 1 ST7MC1/st7mc2 174/294 motor controller (cont ? d) the figure 96 gives the step ratio register value (left axis) and the number of bemf sampling dur- ing one electrical step with the corresponding ac- curacy on the measure (right axis) as a function of the mechanical frequency. for a given prescaler value (step ratio register) the mechanical frequency can vary between two fixed values shown on the graph as the segment ends. in autoswitched mode, this register is automatical- ly incremented/decremented when the step fre- quency goes out of this segment. at f cpu =4mhz, the range covered by the step ra- tio mechanism goes from 2.39 to 235000 (pole pair x rpm) with a minimum accuracy of 1.2% on the step period. to read the number of samples for zn within one step (right y axis), select the mechanical frequen- cy on the x axis and the sampling frequency curve used for bemf detection (pwm frequency or measurement window frequency). for example, for n.frpm = 15,000 and a sampling frequency of 20khz, there are approximately 10 samples in one step and there is a 10% error rate on the measure- ment. figure 96. step ratio bits decoding and accuracy results and bemf sampling rate step ratio (decimal) n.frpm 1 2.39 4.79 7.18 9.57 14.4 19.1 28.7 38.3 57.4 76.6 115 153 230 306 460 614 920 1230 1840 2450 3680 4900 7350 9800 14700 19600 29400 39200 58800 78400 118000 157000 235000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 avg zn ~ 7fh 0.6% 100% bemf samples ? zn/zn 0% 10% 50% 1 2 4 10 200 hz 20 khz avg zn ~ ffh 0.4% avg zn ~ 7fh 0.6% avg zn ~ ffh 0.4% avg zn ~ 55h 1.2% fn 3.fn fn+1 = 2.fn 3.fn+1 = 6.fn f step = 6.n.f rpm = n.f / 10 ? n.f = 10.f step n: pole pair number f step : electrical step frequency st[3:0] avg zn ~ 55h 1.2% 1 ST7MC1/st7mc2 175/294 motor controller (cont ? d) table 40. step frequency/period range (4mhz) table 41. modes of accessing mtim timer-related registers step ratio bits st[3:0] in mprsr register maximum step frequency minimum step frequency minimum step period maximum step period 0000 23.5 khz 7.85 khz 42.5 s127.5 s 0001 11.7 khz 3.93 khz 85 s255 s 0010 5.88 khz 1.96 khz 170 s510 s 0011 2.94 khz 980 hz 340 s1.02ms 0100 1.47 khz 490 hz 680 s2.04ms 0101 735 hz 245 hz 1.36 ms 4.08 ms 0110 367 hz 123 hz 2.72 ms 8.16 ms 0111 183 hz 61.3 hz 5.44 ms 16.32 ms 1000 91.9 hz 30.7 hz 10.9 ms 32.6 ms 1001 45.9 hz 15.4 hz 21.8 ms 65.2 ms 1010 22.9 hz 7.66 hz 43.6 ms 130 ms 1011 11.4 hz 3.83 hz 87 ms 261 ms 1100 5.74 hz 1.92 hz 174 ms 522 ms 1101 2.87 hz 0.958 hz 349 ms 1.04 s 1110 1.43 hz 0.479 hz 697 ms 2.08 s 1111 0.718 hz 0.240 hz 1.40 s 4.17 s state of mcra / mcrb / mpar register bits access to mtim timer related registers rst bit tes[1:0] swa bit cke bit mode read only access read / write access 0 xx x 0 configuration mode mtim, mtiml, mzprv, mzreg, mcomp, mdreg, st[3:0] 0 00 0 1 switched mode mtim, st[3:0] mcomp, mdreg, mzreg, mzprv rmi bit of misr: 0: no action 1: decrement st[3:0] rpi bit of misr: 0: no action 1: increment st[3:0] 0 00 1 1 autoswitched mode mtim, st[3:0] mdreg, mcomp, mzreg, mzprv, rmi, rpi bit of misr: set by hardware, (increment st[3:0]) cleared by software 0 01 10 11 x 1 speed sensor mode mtim, mtiml, st[3:0] mdreg,mzreg, mzprv, rmi, rpi bit of misr, : set by hardware, (increment or decre- ment st[3:0]), cleared by software. 1 ST7MC1/st7mc2 176/294 motor controller (cont ? d) 9.6.7.5 speed measurement mode motor speed can be measured using two methods depending on sensor type: period measurement or pulse counting. typical sensor handling is de- scribed here. incremental encoders allows accurate speed measurement by providing a large number of puls- es per revolution (ppr) with ppr rates up to several thousands; the higher the ppr rate, the higher the resolution. the proposed method consists of counting the number of clock cycles issued by the incremental encoder interface (encoder clock) during a fixed time window (refer to figure 98 ). the tachogenerator has a much lower ppr rate than the encoder (typically factor 10). in this con- text, it is more meaningful to measure the period between tacho captures (i.e. relevant transitions of the incoming signals). accuracy is imposed by the reference clock, i.e. the cpu clock (refer to figure 97 ). figure 97. tachogenerator period acquisition using mtim timer figure 98. encoder clock frequency measure using mtim timer c s c c c c c c comparator output tacho capture compare value mtim counter value interrupts decreasing speed s c to interrupt generator to interrupt generator (capture event) (speed error event) encoder clock capture (triggered by software mtim counter value c c c c c c c interrupts decreasing speed c to interrupt generator (capture event) or real time clock) 1 ST7MC1/st7mc2 177/294 motor controller (cont ? d) hall sensors (or equivalent sensors providing posi- tion information) are widely used for motor control. there are two cases to be considered: ? bldc motor or six-step synchronous motor drive; ? sensor mode ? is recommended in this case, as most tasks are performed by hardware in the delay manager ? blac, asynchronous or motors supplied with 3- phase sinewave-modulated pwm signals in gen- eral; in this case ? speed sensor mode ? allows high accuracy speed measurement (the sensor mode of the delay manager being unsuitable for sinewave generation). position information is handled by software to lock the statoric field to the rotoric one for driving synchronous motors. hall sensors are usually arranged in a 120 config- uration. in that case they provide 3 ppr with both rising and falling edge triggering; the tachogenera- tor measurement method can therefore be ap- plied. the main difference lies in the fact that one must use the position information they provide. this can be done using the three mcix pins and the analog multiplexer to know which of the 3 sen- sors toggled; an interrupt is generated just after the expected transition (refer to figure 99 ). as described in figure 100 , the mtim timer is re- configured depending on the selected sensor. this means that most of delay manager registers are used for a different purpose, with modified func- tionalities. for greater precision, the mtim up-counter is ex- tended to 16 bits using mtim and an additional mtiml register. on a capture event, the current counter value is captured and the counter [mtim:mtiml] is cleared. the counting direction is not affected by the edir bit when using an en- coder sensor. a 16-bit capture register is used to store the cap- tured value of the extended mtim counter: the speed result will be either a period in clock cycles or a number of encoder pulses. this 16-bit register is mapped in the mzreg and mzprv register ad- dresses. to ensure that the read value is not cor- rupted between the high and low byte accesses, a read access to the msb of this register (mzreg) locks the lsb (ie mzprv content is locked) until it is read and any other capture event in between these two accesses is discarded. a compare unit allows a maximum value to be en- tered for the tacho periods. if the 16-bit counter [mtim:mtiml] exceeds this value, a speed error interrupt is generated. this may be used to warn the user that the tachogenerator signal is lost (wires disconnected, motor stalled,...). as 8-bit ac- curacy is sufficient for this purpose, only the ms- byte of the counter (i.e. mtim) is compared to 8-bit compare register, mapped in the mdreg register location. the lsbyte is nevertheless compared with a fixed ffh value. available values for com- parison are therefore ffffh, feffh, fdffh, ..., 01ffh, 00ffh. note : this functionality is not useful when using an encoder. with an encoder, user must monitor the captured values by software during the period- ic capture interrupts: for instance, when driving an ac motor, if the values are too low compared to the stator frequency, a software interrupt may be triggered. figure 99. hall sensor period acquisition using mtim timer 1 mechanical cycle mcia: hall sensor 1 mcib: hall sensor 2 mcic: hall sensor 3 tacho capture period measurements c c c c c c c c c c c c c interrupts 1-2 3-1 2-3 3-1 1-2 2-3 1 ST7MC1/st7mc2 178/294 motor controller (cont ? d) figure 100. overview of mtim timer in speed measurement mode s c = register updated on r event to interrupt generator to interrupt generator s compare clock msbits clr c c 16-bit up counter mtim mtiml 16-bit capture register mzreg mzprv lsbits c mdreg (16mhz) st[3:0] bits 4 1 / 2 ratio mzreg < 55h? mtim register = ffh? +1 -1 tratio rpi rmi mprsr register is[1:0] bits encoder clock tes[1:0] bits mpar* and mphst* is[1:0] tes[1:0] registers: mzfr* mphst* mpar* ecm c tacho capture mtim read access rtc interrupt (capture event) (speed error event) compare ffh (fixed) 16 mhz - 500 hz rpi to interrupt generator rmi to interrupt generator (ratio increment event) (ratio decrement event) bits: registers notes: * = register set-up described in speed sensor mode section (4mhz) f mtc f periph 1 ST7MC1/st7mc2 179/294 motor controller (cont ? d) a logic block manages capture operations de- pending on the sensor type. a capture is initiated on an active edge ( ? tacho capture ? event) when using a tachogenerator. if an encoder is used, the capture is triggered on two events depending on the encoder capture mode bit (ecm) in the mzfr register: ? reading the msb of the counter in manual mode (ecm = 1) ? interrupt from the real time clock in automat- ic mode (ecm = 0) the clock source of the counter is selected de- pending on sensor type: ? motor control peripheral clock (16 mhz) with tachogenerator or hall sensors ? encoder clock in order to optimize the accuracy of the measure- ment for a wide speed range, the auto-updated prescaler functionality is used with slight modifica- tions compared to sensor/sensorless modes (re- fer to figure 101 and table 38 ). ? when the [mtim:mtiml] timer value reaches ffffh, the prescaler is automatically increment- ed in order to slow down the counter and avoid an overflow. to keep consistent values, the mtim and mtiml registers are shifted right (di- vided by two). the rpi bit in the misr register is set and an interrupt is generated (if rim is set). ? when a capture event occurs, if the [mtim:mtiml] timer value is below 5500h, the prescaler is automatically decremented in order to speed up the counter and keep precision bet- ter than 0.005% (1/5500h). the mtim and mtiml registers are shifted left (multiplied by two). the rmi bit in the misr register is set and an interrupt is generated if rim is set. ? if the prescaler contents reach the value 0, it can no longer be automatically decremented, the [mtim:mtiml] timer continues working with the same prescaler value, i.e. with a lower accuracy. no rmi interrrupt can be generated. ? if the prescaler contents reach the value 15, it can no longer be automatically incremented. when the timer reaches the value ffffh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer clock is disabled, and its contents stay at ffffh. the capture logic block still works, ena- bling the capture of the maximum timer value. the only automatically updated registers for the speed sensor mode are mtim and mtiml. ac- cess to delay manager registers in speed sensor mode is summarised in table 41 . figure 101. auto-updated prescaler functional diagram ratio > 0? ratio = ratio - 1 counter = 0 begin end yes no capture with [mtim:mtiml] timer < 5500h ratio < fh? ratio = ratio + 1 counter = counter/2 begin end yes no [mtim:mtiml] timer overflow slow-down control speed-up control (mtim = mtiml = ffh) (mzreg < 55h) 1 ST7MC1/st7mc2 180/294 motor controller (cont ? d) three kinds of interrupt can be generated in speed sensor mode, as summarized in figure 102 : ? c interrupt, when a capture event occurs; this in- terrupt shares resources (mask bit and flag) with the commutation event in switched/au- toswitched mode, as these modes are mutually exclusive. ? rpi/rmi interrupts occur when the st[3:0] bits of the mpsr register are changed, either automat- ically or by hardware. ? s interrupt occurs when a speed error happens (i.e. a successful comparison between [mtim:mtiml] and [mdreg:ff]). this interrupt has the same channel as the emergency stop in- terrupt (mces), as it also warns the user about abnormal system operation. the respective flag bits have to be tested in the interrupt service rou- tine to differentiate speed errors from emergen- cy stop events. these interrupts may be masked individually. note on delay manager initialization in speed measurement mode: in order to set-up the [mtim:mtiml] counter properly before any speed measurement, the following procedure must be applied: ? the peripheral clock must be disabled (resetting the cke bit in the mcra register) to allow write access to st[3:0], mtim and mtiml (refer to ta- ble 41 ), ? mtim, mtiml must be reset and appropriate val- ues must be written in the st[3:0] prescaler adapt to the frequency of the signal being meas- ured and to allow speed measurement with suffi- cient resolution. note on mtiml: the least significant byte of the counter (mtiml) is not used when working in po- sition sensor or sensorless modes. debug option: a signal reflecting the capture events may be output on a standard i/o port for de- bugging purposes. refer to section 9.6.7.3 on page 168 for more details. figure 102. prescaler auto-change example c c c c c rpi rmi c apture ffffh faffh 8000h 5500h s e vents u sual working range c rpi s events: capture speed error ratio increment rmi ratio decrement notes: [mtim:mtiml] [mtim:mtiml] input clock: f x f x / 2 (st[3:0] = n) (st[3:0] = n+1) 1 ST7MC1/st7mc2 181/294 motor controller (cont ? d) 9.6.7.6 summary the use of the delay manager registers for the various available modes is summarized in table 42 . table 42. mtim timer-related registers 9.6.8 pwm manager the pwm manager controls the motor via the six output channels in voltage mode or current mode depending on the v0c1 bit in the mcra register. a block diagram of this part is given in figure 104 . 9.6.8.1 voltage mode in voltage mode (v0c1 bit = ? 0 ? ), the pwm signal which is applied to the switches is generated by the 12-bit pwm generator compare u. its duty cycle is programmed by software (refer to the pwm generator section) as required by the application (speed regulation for example). the current comparator is used for safety purpos- es as a current limitation. for this feature, the de- tected current must be present on the mccfi pin and the current limitation must be present on pin mccref. this current limitation is fixed by a volt- age reference depending on the maximum current acceptable for the motor. this current limitation is generated with the v dd voltage by means of an external resistor divider but can also be adjusted with an external reference voltage ( 5 v). the ex- ternal components are adjusted by the user de- pending on the application needs. in voltage mode, it is mandatory to set a current limitation. as this limitation is set for safety purposes, an inter- rupt can be generated when the motor current feedback reaches the current limitation in voltage mode. this is the current limitation interrupt and it is enabled by setting the corresponding clm bit in the mimr register. this is useful in voltage mode for security purposes. the pwm signal is directed to the channel manag- er that connects it to the programmed outputs (see figure 104 ). name reset value switched / auto switched mode speed measurement mode mtim 00h timer value 16-bit timer msb value mtiml 00h n/a 16-bit timer lsb value mzreg 00h capture/compare zn capture of 16-bit timer msb mzprv 00h capture zn-1 capture of 16-bit timer lsb mcomp 00h compare cn+1 n/a mdreg 00h demagnetization dn compare for speed error interrupt generation 1 ST7MC1/st7mc2 182/294 motor controller (cont ? d) 9.6.8.2 over current handling in voltage mode when the current limitation interrupt is enabled by setting the clim bit in the mimr register (available only in voltage mode), the ocv bit in mcrb reg- ister will determine the effect of this interrupt on the mcox outputs as shown in table 43 . table 43. ocv bit effect for safety purposes, it can be necessary to put all mcox outputs in reset state (high impedance or low state depending on the diss bit in the mscr register) on a current limitation interrupt. this is the purpose of the ocv bit. when a current limita- tion interrupt occurs, if the ocv bit is reset, the ef- fect on the mcox outputs is only to put the pwm signal off on the concerned outputs. if the ocv bit is set, when the current limitation interrupt oc- curs, all the mcox outputs are put in reset state. 9.6.8.3 current mode in current mode, the pwm output signal is gener- ated by a combination of the output of the meas- urement window generator (see figure 105 ) and the output of the current comparator, and is direct- ed to the output channel manager as well ( figure 106 ). the current reference is provided to the compara- tor by phase u, v or w of the pwm generator (up to 12-bit accuracy) the signal from the three com- pare registers u, v or w can be output by setting the pwmu, pwmv or pwmw bits in the mpwme register. the pwm signal is filtered through an ex- ternal rc filter on pin mccref. the detected current input must be present on the mccfi pin. 9.6.8.4 current feedback comparator two programmable filters are implemented: ? a blanking window ( current window filter) after pwm has been switched on to avoid spurious pwm off states caused by parasitic noise ? an event counter (current feedback filter) to prevent pwm being turned off when the first comparator edge is detected. figure 103. current window and feedback filters clim bit cli bit ocv bit output effect interrupt 00x normal running mode no 01x pwm is put off on current loop effect no 10x normal running mode no 110 pwm is put off on current loop effect yes 111 all mcox outputs are put in reset state (moe reset) yes pwm on no end of blanking window ? current > limit ? limit=1? reset counter increment counter set the cl bit counter= no no yes yes no yes window filter feedback filter limit? current current yes 1 ST7MC1/st7mc2 183/294 motor controller (cont ? d) table 44. current window filter setting note: times are indicated for 4 mhz f periph the current window filter is activated each time the pwm is turned on. it blanks the output of the current comparator during the time set by the cfw[2:0] bits in the mcfr register. the reset val- ue is 000b (blanking window off). the current feedback filter sets the number of consecutive valid samples (when current is above the limit) needed to generate the active cl event used to turn off the pwm. the reset value is 1. the sampling of the current comparator is done at f periph /4. table 45. current feedback filter setting the on time of the resulting pwm starts at the end of the measurement window (rising edge), and ends either at the beginning of the next meas- urement window (falling edge), or when the cur- rent level is reached. note: be careful that the current comparator is off until the cke and/or dac bits are set in the mcra register. cfw2 cfw1 cfw0 blanking window length 0 0 0 blanking window off 001 0.5 s 010 1 s 011 1.5 s 100 2 s 101 2.5 s 110 3 s 111 3.5 s cff2 cff1 cff0 nb of feedback samples needed to turn off pwm 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 1 ST7MC1/st7mc2 184/294 motor controller (cont ? d) 9.6.8.5 current feedback amplifier in both current and voltage mode, the current feedback from the motor can be amplified before entering the comparator. this is done by an inte- grated op-amp that can be used when the oaon bit is set in the oacsr register and the cfav bit in the mref register is reset. this allows the three points of the op-amp to be accessed for a pro- grammable gain. the cfav bit in the mref regis- ter selects the mccfi or oaz pin as the compara- tor input as shown in the following table. table 46. comparator input selection if the amplifier is not used for current feedback, it can be used for other purposes. in this case, the oaon bit in the oacsr register and the cfav bit in the mref register both have to be set. this means that the current feedback has to be on the mccfi pin to be directly connected to the compa- rator and the oap, oan and oaz pins can be used to amplify another signal. both the oaz and mccfi pins can be connected to an adc entry. see ( figure 104 ). note: the mccfi pin is not available in tqfp32; sdip32 and tqfp44 devices. in this case, the cfav bit must be reset. the choice to use the op- amp or not is made with the oaon bit. 9.6.8.6 measurement window in current mode, the measurement window fre- quency can be programmed between 390hz and 50khz by the means of the sa[3:0] bits in the mprsr register. note: these frequencies are given for a 4 mhz peripheral input frequency for a bldc drive (xt16, xt8 bits in mconf register). in sensorless mode this measurement window can be used to detect bemf zero crossing events. its width can be defined between 2.5 s and 40 s as a minimum in sensorless mode by the ot[3:0] bits in the mpwme register. figure 104. current feedback cfav bit meaning 0 select oaz as the current comparator in- put 1 select mcccfi as the current compara- tor input oaz filter v cref 12-bit pwm generator mccref c ext v cref max = v dd power down mode to phase state cfw[2:0] bits control (v) r 1ext r 2ext v dd (i) legend : (i): current mode (v): voltage mode cli: current limitation inter- rupt + - oaon bit oacsr register v i 12-bit pwm generator/compare u sampling frequency v0c1 bit mcra register internal clock mcfr register d cp s q q r oan oap mcpwmu/v/w + - pwme[u:v:w] bit mref register mccfi cfav bit mref register adc cli cff[2:0] bits mcfr register 1 ST7MC1/st7mc2 185/294 motor controller (cont ? d) this sets the minimum off time of the pwm signal generated by this internal clock. this off time can vary depending on the output of the current feed- back comparator. in sensor mode (sr=1) and when the sampling for the z event is done during the pwm on time in sensorless mode (splg bit is set in mcrc register and /or ds[3:0] bits with a value other than 000 in mconf register), there is no minimum off time required anymore, the min- imum off time is set automatically to 0s and the off time of the pwm signal is controlled only by the current regulation loop. table 47. sampling frequency selection note: times are indicated for 4 mhz f periph warning : if the off time value set is superior than the period of the pwm signal (for example 40s off time for a 50khz(25s period) pwm frequency), then the signal output on mcox pins selected is a 100% duty cycle signal (always at 1). table 48. off time table note: times are indicated for 4 mhz f periph figure 105. sampling clock generation block sa3 sa2 sa1 sa0 sampling frequency 0000 50.0 khz 0001 40.0 khz 0010 33.33 khz 0011 25.0 khz 0100 20.0 khz 0101 18.1 khz 0110 15.4 khz 0111 12.5 khz 1000 10 khz 1001 6.25 khz 1010 3.13 khz 1011 1.56 khz 1100 1.25 khz 1101 961 hz 1110 625 hz 1111 390 hz ot3 ot2 ot1 ot0 off time sen- sorless mode (sr=0) (ds[3:0]=0) sensor mode (sr=1) or sam- pling during on time in sensor- less (splg =1 and/or ds[3:0] bits) 0 0 0 0 2.5 s no minimum off time 00 0 1 5 s 0 0 1 0 7.5 s 0 0 1 1 10 s 0 1 0 0 12.5 s 0 1 0 1 15 s 0 1 1 0 17.5 s 0 1 1 1 20 s 1 0 0 0 22.5 s 1 0 0 1 25 s 1 0 1 0 27.5 s 1 0 1 1 30 s 1 1 0 0 32.5 s 1 1 0 1 35 s 1 1 1 0 37.5 s 1 1 1 1 40 s frequency logic f periph off-time logic s q r 4 sa[3:0] bits 2 ot[3:0] bits t off t sampling note: the mtc controller input frequency ( f periph ) is 4 mhz in this example, . mprsr register mpwme register it can be configured to 8mhz with the xt16: xt8 bits in the mconf register (measurement window) 1 ST7MC1/st7mc2 186/294 motor controller (cont ? d) 9.6.9 channel manager the channel manager consists of: ? a phase state register with preload and polarity function ? a multiplexer to direct the pwm to the low and/ or high channel group ? a tristate buffer asynchronously driven by an emergency input the block diagram is shown in figure 106 . figure 106. channel manager block diagram cff[2:0] bits oo bits* c oe[5:0] bits 6 6 os[2:0] bits* phase n register* sr bit 3 pwm generator sampling frequency dac bit channel [5:0] current comparator output v i pwm generator sq r v0c1 bit v i filter op[5:0] bits moe bit mco0 mco1 mco2 mco3 mco4 mco5 nmces x6 x6 6 1 mphst register mpol register mcrb register mpar register * = preload register, changes taken into account at next c event. mcra register mcra register mcra register mcra register mcfr register reg c d s,h z events: commutation befm z ero-crossing end of d emagnetization e emergency stop notes: updated/shifted on r ratio updated (+1 or -1) multiplier o verflow r +/- o c urrent mode v oltage mode i v reg n updated with reg n+1 on c 1 2 branch taken after c event branch taken after d event channel [5:0] dead time dead time dead time 8 mdtg register 2 6 high frequency chopper hfe[1:0] bits hfrq[2:0] bits mref register 5 cli bit clim bit ocv bit 1 1 1 1 ST7MC1/st7mc2 187/294 motor controller (cont ? d) 9.6.9.1 mphst phase state register a preload register enables software to asynchro- nously update the channel configuration for the next step (during the previous commutation inter- rupt routine for example): the oo[5:0] bits in the mphst register are copied to the phase register on a c event. table 49. output state direct access to the phase register is also possible when the dac bit in the mcra register is set. note 1: in direct access mode (dac bit is set in mcra register), a c event is generated as soon as there is a write access to oo[5:0] bits in mphst register. note 2: in direct access mode (dac bit is set in mcra register) the pwm application is selected by the os0 bit in the mcrb register. table 50. dac and moe bit meaning *note: the reset state of the outputs can be either high impedance, low or high state depending on the corresponding option bit. the polarity register is used to match the polarity of the power drivers keeping the same control log- ic and software. if one of the opx bits in the mpol register is set, this means the switch x is on when mcox is v dd . each output status depends also on the momen- tary state of the pwm, its group (low or high), and the peripheral state. pwm features the outputs can be split in two pwm groups in or- der to differentiate the high side and the low side switches. this output property can be pro- grammed using the oe[5:0] bits in the mpar reg- ister. table 51. meaning of the oe[5:0] bits the multiplexer directs the pwm to the upper channel, the lower channel or both of them alter- natively or simultaneously according to the periph- eral state. this means that the pwm can affect any of the up- per or lower channels allowing the selection of the most appropriate reference potential when free- wheeling the motor in order to: ? improve system efficiency ? speed up the demagnetization phase ? enable back emf zero crossing detection. the os[2:0] bits in the mcrb register allow the pwm configuration to be configured for each case as shown in figure 108 and figure 107 . during demagnetization, the os2 bit is used to control pwm mode, and it is latched in a preload register so it can be modified when a commutation event occurs and the configuration is active imme- diately. the os1 bit is used to control the pwm between the d and z events to control back-emf detection. os0 bit will allow to control the pwm signal be- tween z event and next c event. note about demagnetization speed-up: during demagnetization the voltage on the winding has to be as high as possible in order to reduce the de- magnetization time. software can apply a different pwm configuration on the outputs between the c and d events, to force the free wheeling on the ap- propriate diodes to maximize the demagnetization voltage. 9.6.9.2 emergency feature when the nmces pin goes low ? the tristate output buffer is put in reset state asynchronously ? the moe bit in the mcra register is reset ? an interrupt request is sent to the cpu if the eim bit in the mimr register is set this bit can be connected to an alarm signal from the drivers, thermal sensor or any other security component. this feature functions even if the mcu oscillator is off. op[5:0] bit oo[5:0] bit mco[5:0] pin 0 0 1 (off) 0 1 0-(pwm allowed) 1 0 0 (off) 1 1 1-(pwm allowed) moe bit dac bit effect on output 0 x reset state* 10 standard running mode 11 mphst register value (depending on mpol, mpar register values and pwm setting) see table 75 oe[5:0] channel group 0 high channel 1 low channel 1 ST7MC1/st7mc2 188/294 motor controller (cont ? d) figure 107. pwm application in voltage or current sensorless mode (see table 62 ) step os2 pwm behaviour after c 0 1 high channels low channels voltage (v0c1=x) off (0) x 1 0 on (1) cn d cn+1 m o d e o o [ 5 : 0 ] demagnetization e v e n t o s [ 2 : 0 ] 000 low 001 high low 010 011 high low high low 100 101 110 111 o e [ 5 : 0 ] high 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x and before d os1 pwm behaviour after d 0 1 high channels low channels and before z os0 pwm behaviour after z 0 1 high channels low channels and before next c z demagnetization demagnetization wait z event delay high low high low high low high low os2 os1 os0 1 ST7MC1/st7mc2 189/294 motor controller (cont ? d) figure 108. pwm application in voltage or current sensor mode (see table 63 ) cn cn+1 m o d e voltage (v0c1=x) o s [ 2 : 0 ] o o [ 5 : 0 ] x (sensor mode: sr=1) step e v e n t off (0) on (1) xx 0x0 1 0 - in sensor mode, there is no demagnetisation event and the pwm behaviour can be changed before and after z event z os2 pwm behaviour after c 0 1 high channels low channels and before z os1 not used os0 pwm behaviour after z 0 1 high channels low channels and before next c os2 os0 wait z event delay delay o e [ 5 : 0 ] x 0x1 1x0 1x1 0 1 0 1 0 1 0 1 high low high low high low high low 1 ST7MC1/st7mc2 190/294 motor controller (cont ? d) 9.6.9.3 dead time generator when using typical triple half bridge topology for power converters, precautions must be taken to avoid short circuits in half bridges. this is ensured by driving high and low side switches with comple- mentary signals and by managing the time be- tween the switching-off and the switching-on in- stants of the adjacent switches. this time is usually known as deadtime and has to be adjusted depending on the devices connected to the pwm outputs and their characteristics (in- trinsic delays of level-shifters, delays due to power switches,...). when driving motors in six-step mode, the dead- time generator function also allows synchronous rectification to be performed on the switch adja- cent to the one where pwm is applied to reduce conduction losses. for each of the three pwm channels, there is one 6-bit dead time generator available. it generates two output signals: a and b. the a output signal is the same as the input phase signal except for the rising edge, which is delayed relative to the input signal rising edge. the b output signal is the opposite of the input phase signal except the rising edge which is de- layed relative to the input signal falling edge. figure 109 shows the relationship between the output signals of the deadtime register and its in- puts. if the delay is greater than the width of the active phase (a or b) then the corresponding pulse is not generated (see figure 110 and figure 111 ). figure 109. dead time waveforms figure 110. dead time waveform with delay greater than the negative pwm pulse reference output a output b delay delay 5v 5v 5v 0v 0v 0v input signal input output a output b delay 5v 5v 5v 0v 0v 0v 1 ST7MC1/st7mc2 191/294 motor controller (cont ? d) figure 111. dead time waveform with delay greater than the positive pwm pulse table 52. dead time programming and example the deadtime delay is the same for each of the channels and is programmable with the dtg[5..0] bits in the mdtg register. the resolution is variable and depends on the dtg5 and dtg4 bits. table 52 summarizes the set-up of the deadtime generator. i t mtc is the period of the dead time generator in- put clock ( f mtc = 16 mhz in most cases, not affect- ed by the xt16:xt8 prescaler bits in the mconf register). for safety reasons and since the deadtime de- pends only on external component characteristics (level-shifter delay, power components switching duration,...) the register used to set-up deadtime duration can be written only once after the mcu reset. this prevents a corrupted program counter modifying this system critical set-up, which may cause excessive power dissipation or destructive shoot-through in the power stage half bridges. when using the three independent u, v and w pwm signals (pcn bit set) (see figure 112 ) to drive the mcox outputs, deadtime is added as shown in figure 109 . the dead time generator is enabled/disabled us- ing the dte bit. the effect of the dte bit depends on the pcn bit value. if the pcn bit is set: dte is read only. to reset it, first reset the pcn bit, then reset dte and set pcn to 1 again. if dte=0, the high and low side outputs are simply complemented (no deadtime insertion, dtg[5:0] bits are not significant); this is to allow the use of an external dead time generator. note: the reset value of the mdtg register is ffh so when configuring the dead time, it is mandatory to follow one the two following sequences: to use dead t imes while the pcn bit is set; from reset state write the mdtg value at once. the dte bit will be read back as 1 whatever the programming value (read only if pcn=1) to use dead times while the pcn bit is reset, write first the dead time value in dtg[5:0], then reset the pcn bit, or do both actions at the same time. dtg5 dtg4 t dtg deadtime expression deadtime value t dtg @16mhz f mtc dead time range @ 16mhz f mtc 0x2xt mtc (dtg[4..0]+1) x t dtg from 1 to 32 t dtg 125ns 0.125s to 4s 104xt mtc (dtg[3..0]+1) x t dtg from 17 to 31 t dtg 250ns 4.25s to 8s 118xt mtc 500ns 8.5s to 16s input output a output b delay 5v 5v 5v 0v 0v 0v 1 ST7MC1/st7mc2 192/294 motor controller (cont ? d) figure 112. channel manager output block diagram with pwm generator delivering 3 pwm signals dead time dead time dead time 8 mdtg register u v w pwm generator signals pcn bit = 1 op[5:0] bits moe bit mco0 mco1 mco2 mco3 mco4 mco5 nmces x6 x6 6 1 mpol register mrca register channel [1:0] channel [3:2] channel [5:4] 2 high frequency chopper hfe[1:0] bits hfrq[2:0] bits mref register 5 cli bit clim bit ocv bit 1 1 1 1 ST7MC1/st7mc2 193/294 motor controller (cont ? d) if the pcn bit is reset, one of the three pwm sig- nals (the one set by the compare u register pair) or the output of the measurement window generator (depending on if the driving mode is voltage or cur- rent) is used to provide six-step signals through the pwm manager (to drive a pm bldc motor for instance). in that case, dte behaves like a standard bit (with multiple write capability). when the deadtime gen- erator is enabled (bit dte=1), some restrictions are applied, summarized in table 53 : channels are now grouped by pairs: channel[0:1], channel[2:3], channel[4:5]; a deadtime generator is allocated to each of these pairs (see cautions below); the input signal of the deadtime generator is the active output of the pwm manager for the corresponding channel. for instance, if we consider the channel[0:1] pair, it may be either channel0 or channel1. when both channels of a pair are inactive, the corresponding outputs will also stay inactive (this is mandatory to allow bemf zero-crossing detection). table 53 summarizes the functionality of the dead- time generator when the pcn bit is reset. 1(pwm*) means that the corresponding channel is active (1 in the corresponding bit in the mphst register), and a pwm signal is applied on it (using the mpar register and the os[2:0] bits in mcrb register). pwm represents the complementary signals (al- though the duty cycle is slightly different due to deadtime insertion). 0 means that the channel is inactive and 1 means that the channel is active and a logic level 1 is applied on it (no pwm signal). table 53. dead time generator outputs * pwm generation enabled warning: grouping channels by pairs imposes the external connections between the mco outputs and power devices; the user must therefore pay at- tention to respect the ? recommended schematics ? described in figure 121. on page 224 and figure 122 note: as soon as the channels are grouped in pairs, special care has to be taken in configuring the mpar register for a pm bldc drive. if both channels of the same pair are both labelled ? high ? for example and if the pwm is applied on high channels, the active mco output x (oox=1 bit in the mphst register) outputs pwm and the paired mco output x+1 (oox+1bit in the mphst regis- ter) outputs pwm and vice versa. caution: when pcn=0 and a complementary pwm is applied (dte=1) on one channel of a pair, if both channels are active, this corresponds in output to both channels off. this is for security purpose to avoid cross-conduction. caution: to clear the dte bit from reset state of mdtg register (ffh), the pcn bit must be cleared before. pcn = 0; dte =1; x= 0, 2, 4 on/off x (oox bit) on/off x+1 (oox+1 bit) mcox output mcox+1 output 01 (pwm*)pwm pwm 1 (pwm*) 0 pwm pwm 11 (pwm*) 0 0 1 (pwm*) 1 0 0 10 1 0 01 0 1 00 0 0 1 ST7MC1/st7mc2 194/294 motor controller (cont ? d) figure 113. channel manager output block diagram with pwm generator delivering 1 pwm signal dead time dead time dead time 8 mdtg register ch0 ch1 ch2 ch3 ch4 ch5 pcn bit = 0 op[5:0] bits moe bit mco0 mco1 mco2 mco3 mco4 mco5 nmces x6 x6 6 1 mpol register mcra register channel [1:0] channel [3:2] channel [5:4] phase n register* pwm generator sampling frequency v i s q r v i u channel high frequency chopper oe[5:0] bits 6 mpar register 6 2 hfe[1:0] bits hfrq[2:0] bits mref register 5 current comparator output cli bit clim bit ocv bit 1 1 1 1 ST7MC1/st7mc2 195/294 motor controller (cont ? d) 9.6.9.4 programmable chopper depending on the application hardware, a chopper may be needed for the pwm signal. the mref register allows the chopping frequency and mode to be programmed. the hfe[1:0] bits program the channels on which chopping is to be applied. the chopped pwm sig- nal may be needed for high side switches only, low side switches or both of them in the same time (see table 54 ). table 54. chopping mode the chopping frequency can any of the 8 values from 100khz to 2mhz selected by the hfrq[2:0] bits in the mref register (see table 55 ). table 55. chopping frequency note: when the pcn bit = 0: ? if complementary pwm signals are not applied (dte bit = 0), the high and low drivers are fixed by the mpar register. figure 106 , figure 112 and figure 113 indicate where the hfe[1:0] bits are taken into account depending on the pwm application. ? if complementary pwm signals are applied (dte bit = 1), the channels are paired as explained in ? dead time generator ? on page 190. this means that the high and low channels are fixed and the hfe[1:0] bits indicate where to apply the chopper. figure 114 shows typical complemen- tary pwm signals with high frequency chopping enabled on both high and low drivers. figure 114. complementary pwm signals with chopping frequency on high and low side drivers. hfe[1:0] bits chopping mode hfe1 hfe0 pcn bit =0 pcn bit =1 00 off off 0 1 low channels only low side switches mco1, 3, 5 1 0 high channels only high side switches mco0, 2, 4 11 both low and high channels both high and low sides hfrq2 hfrq1 hfrq0 chopping frequency f mtc = 16mhz f mtc = 8mhz chopping frequency f mtc = 4mhz 0 0 0 100 khz 50 khz 0 0 1 200 khz 100 khz 0 1 0 400 khz 200 khz 0 1 1 500 khz 250 khz 1 0 0 800 khz 400 khz 1011 mhz500 khz 1 1 0 1.33 mhz 666.66 mhz 1 1 1 2 mhz 1 mhz reference output a output b delay delay 5v 5v 5v 0v 0v 0v input signal 1 ST7MC1/st7mc2 196/294 motor controller (cont ? d) 9.6.10 pwm generator block the pwm generator block produces three inde- pendent pwm signals based on a single carrier frequency with individually adjustable duty cycles. depending on the motor driving method, one or three of these signals may be redirected to the oth- er functional blocks of the motor control peripheral, using the pcn bit in the mdtg register. when driving pm bldc motors in six-step mode (voltage mode only, either sensored or sensor- less) a single pwm signal (phase u) is used to supply the input stage, pwm and channel man- ager blocks according to the selected modes. for other kind of motors requiring independent pwm control for each of the three phases, all pwm signals (phases u, v and w) are directed to the channel manager, in which deadtime or a high frequency carrier may be added. this is the case of ac induction motors or pmac motors for in- stance, supplied with 120 shifted sinewaves in voltage mode. 9.6.10.1 main features 12-bit pwm free-running up/down counter with up to 16mhz input clock ( f mtc ). edge-aligned and center-aligned pwm operating modes possibility to re-load compare registers twice per pwm period in center-aligned mode full-scale pwm generation pwm update interrupt generation 8-bit repetition counter 8-bit pwm mode timer re-synchronisation feature figure 115. pwm generator block diagram mrep register 12-bit compare 0 register 12-bit pwm counter 13-bit compare w register up to 16mhz cms bit 13-bit compare u register 13-bit compare v register u u u u clear or up/down prescaler pcp[2:0] bits u reg u event: update of compare registers notes: preload registers transferred to active registers on u event f mtc mpcr register mpcr register pwm interrupt generation repetition counter 1 ST7MC1/st7mc2 197/294 motor controller (cont ? d) 9.6.10.2 functional description the 3 pwm signals are generated using a free- running 12-bit pwm counter and three 13-bit compare registers for phase u, v and w: mcm- pu, mcmpv and mcmpw registers. a fourth 12-bit register is needed to set-up the pwm carrier frequency: mcmp0 register. each of these compare registers is buffered with a preload register. transfer from preload to active registers is done synchronously with pwm counter underflow or overflow depending on configuration. this allows to write compare values without risks of spurious pwm transitions. the block diagram of the pwm generator is shown on figure 115 . 9.6.10.3 prescaler the 12-bit pwm counter clock is supplied through a 3-bit prescaler to allow the generation of lower pwm carrier frequencies. it divides f mtc by 1, 2, 3, ..., 8 to get f mtc-pwm . this prescaler is accessed through three bits pcp[2:0] in mpcr register; this register is buff- ered: the new value is taken into account after a pwm update event. 9.6.10.4 pwm operating mode the pwm generator can work in center-aligned or edge-aligned mode depending on the cms bit set- ting in the mpcr register. figure 116 shows the corresponding counting se- quence . it offers also an 8-bit mode to get a full 8-bit range with a single compare register write access by set- ting the pms bit in mpcr register. the comparisons described here are performed between the pwm counter value extended to 13 bits and the 13-bit compare register. having a compare range greater than the counter range is mandatory to get a full pwm range (i.e. up to 100% modulation). this principle is maintained for 8-bit pwm operations. center-aligned mode (cms bit = 1) in this operating mode, the pwm counter counts up to the value loaded in the 12-bit compare 0 reg- ister then counts down until it reaches zero and re- starts counting up. the pwm signals are set to ? 0 ? when the pwm counter reaches, in up-counting, the correspond- ing 13-bit compare register value and they are set to ? 1 ? when the pwm counter reaches the 13-bit compare value again in down-counting. figure 116. counting sequence in center-aligned and edge-aligned mode center-aligned mode 0 1 2 .... 15 16 15 .... 2 1 0 1 t edge-aligned mode 0 1 2 ..... 15 16 0 1 ..... 16 0 1 t t = pwm period, value of 12-bit compare 0 register= 16 1 ST7MC1/st7mc2 198/294 motor controller (cont ? d) if the 13-bit compare register value is greater than the extended compare 0 register (the 13 th bit is set to ? 0 ? ), the corresponding pwm output signal is held at ? 1 ? . if the 13-bit compare register value is 0, the corre- sponding pwm output signal is held at ? 0 ? . figure 117 shows some center-aligned pwm waveforms in an example where the compare 0 register value = 8. figure 117. center-aligned pwm waveforms (compare 0 register = 8) 012345678765432101 1 2 3 ? 1 ? 4 ? 0 ? 1 compare register value = 4 2 compare register value = 7 3 compare register value > = 8 4 compare register value = 0 1 ST7MC1/st7mc2 199/294 motor controller (cont ? d) edge-aligned mode (cms bit = 0) in this operating mode, the pwm counter counts up to the value loaded in the 12-bit compare reg- ister. then the pwm counter is cleared and it re- starts counting up. the pwm signals are set to ? 0 ? when the pwm counter reaches, in up-counting, the correspond- ing 13-bit compare register value and they are set to ? 1 ? when the pwm counter is cleared. if the 13-bit compare register value is greater than the extended compare 0 register (the 13 th bit is set to ? 0 ? ), the corresponding pwm output signal is held at ? 1 ? . if the 13-bit compare register value = 0, the corre- sponding pwm output signal is held at ? 0 ? . figure 118 shows some edge-aligned pwm wave- forms in an example where the compare 0 register value = 8. figure 118. edge-aligned pwm waveforms (compare 0 register = 8) 01234567801 1 2 3 ? 1 ? 4 ? 0 ? 1 compare register value = 4 2 compare register value = 8 3 compare register value > 8 4 compare register value = 0 1 ST7MC1/st7mc2 200/294 motor controller (cont ? d) 12-bit mode (pms bit = 0 in the mpcr register) this mode is useful for mcmp0 values ranging from 9 bits to 12 bits. figure 119 presents the way compare 0 and compare u, v, w should be load- ed). it requires loading two bytes in the mcmpxh and mcmpxl registers (i.e. mcmp0, mcmpu, mcmpv and mcmpw 16-bit registers) following the sequence described below: ? write to the mcmpxl register (lsb) first ? then write to the mcmpxh register (msb). the 16-bit value is then ready to be transferred in the active register as soon as an update event oc- curs. this sequence is necessary to avoid poten- tial conflicts with update interrupts causing the hardware transfer from preload to active registers: if an update event occurs in the middle of the above sequence, the update is effective only when the msb has been written. 8-bit pwm mode (pms bit = 1 in mpcr register) this mode is useful whenever the mcmp0 value is less or equal to 8-bits. it allows significant cpu re- source savings when computing three-phase duty cycles during pwm interrupt routines. in this mode, the compare 0 and compare u, v, w reg- isters have the same size (8 bits). the extension of the mcmpx registers is done in using the ovfx bits in the mpcr register (refer to figure 119 ). these bits force the related duty-cycles to 100% and are reset by hardware on occurence of a pwm update event. note about read access to registers with preload: during read accesses, values read are the content of the preload registers, not the active registers. note about compare register active bit loca- tions: the 13 active bits of the mcmpx registers are left-aligned. this allows temporary calculations to be done with 16-bit precision, round-up is done automatically to the 13-bit format when loading the values of the mcmpx registers. note about mcmp0x registers: the configuration mcmp0h=mcmp0l=0 is not allowed figure 119. comparison between 12-bit and 8-bit pwm mode ovfx b0 b7 mcmp0h b0 b7 mcmp0l b0 b7 mcmpxh b0 b7 mcmpxl ext b0 b7 mcmp0h b0 b7 mcmp0l b0 b7 mcmpxh b0 b7 mcmpxl mpcr 12-bit pwm mode (pms bit = 0) 8-bit pwm mode (pms bit = 1) b0 b7 ovfw ovfv ovfu ext bit not available bit extending comparison range equivalent bit location pwm frequency set-up phase x duty cycle set-up pwm frequency set-up phase x duty cycle set-up 1 ST7MC1/st7mc2 201/294 motor controller (cont ? d) 9.6.10.5 repetition down-counter both in center-aligned and edge-aligned modes, the four compare registers (one compare 0 and three for the u, v and w phases) are updated when the pwm counter underflow or overflow and the 8-bit repetition down-counter has reached ze- ro. this means that data are transferred from the preload compare registers to the compare regis- ters every n cycles of the pwm counter, where n is the value of the 8-bit repetition register in edge -aligned mode. when using center-aligned mode, the repetition down-counter is decremented every time the pwm counter overflows or underflows. al- though this limits the maximum number of repeti- tion to 128 pwm cycles, this makes it possible to update the duty cycle twice per pwm period. as a result, the effective pwm resolution in that case is equal to the resolution we can get using edge- aligned mode, i.e. one t mtc period. when refresh- ing compare registers only once per pwm period in center-aligned mode, maximum resolution is 2x t mtc , due to the symmetry of the pattern. the repetition down counter is an auto-reload type; the repetition rate will be maintained as de- fined by the mrep register value (refer to figure 120 ). 9.6.10.6 pwm interrupt generation a pwm interrupt is generated synchronously with the ? u ? update event, which allows to refresh com- pare values by software before the next update event. as a result, the refresh rate for phases duty cycles is directly linked to mrep register setting. a signal reflecting the update events may be out- put on a standard i/o port for debugging purposes. refer to section 9.6.7.3 on page 168 for more de- tails. figure 120. update rate examples depending on mode and mrep register settings center-aligned mode edge-aligned mode u u u u u u event: preload registers transferred to active registers and pwm interrupt generated 12-bit pwm counter mrep = 0 mrep = 1 mrep = 2 mrep = 3 u event if transition from mrep = 0 to mrep = 1 occurs when 12-bit counter is equal to mcp0. u mrep = 3 and re-synchronization (by sw) (by sw) 1 ST7MC1/st7mc2 202/294 motor controller (cont ? d) 9.6.10.7 timer re-synchronisation the 12-bit timer can be re-synchronized by a sim- ple write access with ffh value in the misr regis- ter. re-synchronization means that the 12-bit counter is reset and all the compare preload regis- ters mcp0, mcpu, mcpv, mcpw are transferred to the active registers. to re-synchronize the 12-bit timer properly , the following procedure must be applied: ? 1. load the new values in the preload compare registers ? 2. load ffh value in the misr register (this will reset the counter and transfer the compare preload registers in the active registers: u event) ? 3. reset the pui flag by loading 7fh in the misr register. refer to note 2 on page 205 note: loading ffh value in the misr register will have no effect on any other flag than the pui flag and will generate a pwm update interrupt if the pum bit is set. warning: in switched mode (swa bit is reset), the procedure is the same and loading ffh in the misr register will have no effect on flags except on the pui flag. as a consequence, it is recom- mended to avoid setting rmi and rpi flags at the same time in switched mode because none of them will be taken into account. 9.6.10.8 pwm generator initialization and start- up the three-phase generator counter stays in reset state (i.e. stopped and equal to 0), as long as mtc peripheral clock is disabled (cke = 0). setting the cke bit has two actions on the pwm generator: it starts the pwm counter it forces the update of all registers with preload registers transferred on u update event, i.e. mrep, mpcr, mcmp0, mcmpu, mcmpv, mcmpw (in 12-bit mode, both mcmpxl and mcmpxh must have been written, following the mandatory lsb/msb sequence, before setting cke bit). it consequently generates a u interrupt. 9.6.11 low power modes before executing a halt or wfi instruction, soft- ware must stop the motor, and may choose to put the outputs in high impedance. 9.6.12 interrupts the mtc interrupt events are connected to the three interrupt vectors (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on mtc interface. mtc interrupts exit from wait mode. halt mtc registers are frozen. in halt mode, the mtc interface is in- active. the mtc interface becomes operational again when the mcu is woken up by an interrupt with ? exit from halt mode ? capability. interrupt event event flag enable control bit exit from wait exit from halt ratio increment rpi rim yes no ratio decrement rmi yes no speed error sei sem yes no emergency stop ei eim yes no current limitation cli clim yes no bemf zero-crossing zi zim yes no end of demagnetization di dim yes no commutation or capture ci cim yes no pwm update pui pum yes no 1 ST7MC1/st7mc2 203/294 motor controller (cont ? d) 9.6.13 register description timer counter register (mtim) read /write reset value: 0000 0000 (00h) bits 7:0 = t[7:0] : mtim counter value. these bits contain the current value of the 8-bit up counter. in speed measurement mode, when us- ing encoder sensor and mtim captures triggered by sw (refer to figure 100 ) a read access to mtim register causes a capture of the [mtim:mtiml] register pair to the [mzreg: mzprv] registers. timer counter register lsb (mtiml) read /write reset value: 0000 0000 (00h) bits 7:0 = tl[7:0] : mtim counter value lsb. these bits contain the current value of the least significant byte of the mtim up counter, when used in speed measurement mode (i.e. as a 16-bit timer) capture z n-1 register (mzprv) read /write reset value: 0000 0000 (00h) bits 7:0 = zp[7:0] : previous z value or speed capture lsb. these bits contain the previous captured bemf value (z n-1 ) in switched and autoswitched mode or the lsb of the captured value of the [mtim:mtiml] registers in speed sensor mode. capture z n register (mzreg) read/write reset value: 0000 0000 (00h) bits 7:0 = zc[7:0] : current z value or speed cap- ture msb. these bits contain the current captured bemf val- ue (z n ) in switched and autoswitched mode or the msb of the captured value of the [mtim:mtiml] registers in speed sensor mode. a read access to mzreg in this case disable the speed captures up to mzprv reading (refer to section 9.6.7.5 speed measurement mode on page 176 ). compare c n+1 register (mcomp) read/write reset value: 0000 0000 (00h) bits 7:0 = dc[7:0] : next compare value. these bits contain the compare value for the next commutation (c n+1 ). demagnetization register (mdreg) read/write reset value: 0000 0000 (00h) bits 7:0 = dn[7:0] : d value. these bits contain the compare value for simulat- ed demagnetization (d n ) and the captured value for hardware demagnetization (d h ) in switched and autoswitched mode. in speed sensor mode, the register contains the value used for comparison with mtim registers to generate a speed error event. 76543210 t7 t6 t5 t4 t3 t2 t1 t0 76543210 tl7 tl6 tl5 tl4 tl3 tl2 tl1 tl0 76543210 zp7 zp6 zp5 zp4 zp3 zp2 zp1 zp0 76543210 zc7 zc6 zc5 zc4 zc3 zc2 zc1 zc0 76543210 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 76543210 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 1 ST7MC1/st7mc2 204/294 motor controller (cont ? d) a n weight register (mwght) read/write reset value: 0000 0000 (00h) bits 7:0 = an[7:0] : a weight value. these bits contain the a n weight value for the mul- tiplier. in autoswitched mode the mcomp register is automatically loaded with: when a z event occurs. (*) depending on the dcb bit in the mcra regis- ter. prescaler & sampling register (mprsr) read/write reset value: 0000 0000 (00h) bits 7:4 = sa[3:0] : sampling ratio. these bits contain the sampling ratio value for cur- rent mode. refer to table 47, ? sampling frequen- cy selection, ? on page 185. bits 3:0 = st[3:0] : step ratio. these bits contain the step ratio value. it acts as a prescaler for the mtim timer and is auto incre- mented/decremented with each r+ or r- event. refer to table 40, ? step frequency/period range (4mhz), ? on page 175 and table 41, ? modes of accessing mtim timer-related registers, ? on page 175. interrupt mask register (mimr) read/write reset value: 0000 0000 (00h) bit 7 = pum: pwm update mask bit. 0: pwm update interrupt disabled 1: pwm update interrupt enabled bit 6 = sem: speed error mask bit. 0: speed error interrupt disabled 1: speed error interrupt enabled bit 5 = rim : ratio update interrupt mask bit. 0: ratio update interrupts (r+ and r-) disabled 1: ratio update interrupts (r+ and r-) enabled bit 4 = clim : current limitation interrupt mask bit. 0: current limitation interrupt disabled 1: current limitation interrupt enabled this interrupt is available only in voltage mode (voc1 bit=0 in mcra register) and occurs when the motor current feedback reaches the external current limitation value. bit 3 = eim : emergency stop interrupt mask bit. 0: emergency stop interrupt disabled 1: emergency stop interrupt enabled bit 2 = zim : back emf zero-crossing interrupt mask bit. 0: bemf zero-crossing interrupt disabled 1: bemf zero-crossing interrupt enabled bit 1 = dim : end of demagnetization interrupt mask bit. 0: end of demagnetization interrupt disabled 1: end of demagnetization interrupt enabled if the hdm or sdm bit in the mcrb register is set bit 0 = cim : commutation / capture interrupt mask bit 0: commutation / capture interrupt disabled 1: commutation / capture interrupt enabled 76543210 an7 an6 an5 an4 an3 an2 an1 an0 76543210 sa3 sa2 sa1 sa0 st3 st2 st1 st0 z n x mwght 256(d) or z n -1 x mwght 256(d) (*) 76543210 pum sem rim clim eim zim dim cim 1 ST7MC1/st7mc2 205/294 motor controller (cont ? d) interrupt status register (misr) read/write reset value: 0000 0000 (00h) bit 7 = pui: pwm update interrupt flag. this bit is set by hardware when all the pwm compare register are transferred from the preload to the active registers. the corresponding interrupt allows the user to refresh the preload registers be- fore the next pwm update event defined with mrep register. 0: no pwm update interrupt pending 1: pwm update interrupt pending bit 6 = rpi : ratio increment interrupt flag. autoswitched mode (swa bit =1) : 0: no r+ interrupt pending 1: r+ interrupt pending switched mode (swa bit =0) : 0: no r+ action 1: the hardware will increment the st[3:0] bits when the next commutation occurs and shift all timer registers right. speed sensor mode (swa bit =x, tes[1:0] bits =01, 10, 11) : 0: no r+ interrupt pending 1: r+ interrupt pending bit 5 = rmi : ratio decrement interrupt flag. autoswitched mode (swa bit =1) : 0: no r- interrupt pending 1: r- interrupt pending switched mode (swa bit =0) : 0: no r- action 1: the hardware will decrement the st[3:0] bits when the next commutation occurs and shift all timer registers left. speed sensor mode (swa bit =x, tes[1:0] bits =01, 10, 11) : 0: no r- interrupt pending 1: r- interrupt pending bit 4 = cli : current limitation interrupt flag. 0: no current limitation interrupt pending 1: current limitation interrupt pending bit 3 = ei : emergency stop interrupt flag. 0: no emergency stop interrupt pending 1: emergency stop interrupt pending bit 2 = zi : bemf zero-crossing interrupt flag. 0: no bemf zero-crossing interrupt pending 1: bemf zero-crossing interrupt pending bit 1 = di : end of demagnetization interrupt flag. 0: no end of demagnetization interrupt pending 1: end of demagnetization interrupt pending bit 0 = ci : commutation / capture interrupt flag 0: no commutation / capture interrupt pending 1: commutation / capture interrupt pending note 1 : loading value ffh in the misr register will reset the pwm generator counter and transfer the compare preload registers in the active regis- ters by generating a u event (pui bit set to 1). re- fer to ? timer re-synchronisation ? on page 202. note 2 : in autoswitched mode (swa=1 in the mrca register): as all bits in the misr register are status flags, they are set by internal hardware sig- nals and must be cleared by software. any attempt to write them to 1 will have no effect (they will be read as 0) without interrupt generation. when several mtc interrupts are enabled at the same time the bres instruction must not be used to avoid unwanted clearing of status flags: if a sec- ond interrupt occurs while bres is executed (which performs a read-modify-write sequence) to clear the flag of a first interrupt, the flag of the sec- ond interrupt may also be cleared and the corre- sponding interrupt routine will not be serviced. it is thus recommended to use a load instruction to clear the flag, with a value equal to the logical complement of the bit. for instance, to clear the pui flag: ld misr, # 0x7f. in switched mode (swa=0 in the mrca regis- ter): to avoid any losing any interrupts when modifying the rmi and rpi bits the following instruction se- quence is recommended: ld misr, # 0x9f ; reset both rmi & rpi bits ld misr, # 0xbf ; set rmi bit ld misr, # 0xdf ; set rpi bit 76543210 pui rpi rmi cli ei zi di ci 1 ST7MC1/st7mc2 206/294 motor controller (cont ? d) control register a (mcra) read/write reset value: 0000 0000 (00h) bit 7 = moe: output enable bit. 0: outputs disabled 1: outputs enabled notes: ? the reset state is either high impedance, high or low state depending on the corresponding option bit. ? when the moe bit in the mcra register is reset (mcox outputs in reset state), and the sr bit in the mcra register is reset (sensorless mode) and the splg bit in the mcrc register is reset (sampling at pwm frequency) then, depending on the state of the zsv bit in the mscr register, z event sampling can run or be stopped (and d event is sampled). bit 6 = cke : clock enable bit. 0: motor control peripheral clocks disabled 1: motor control peripheral clocks enabled note: clocks disabled means that all peripheral in- ternal clocks (delay manager, internal sampling clock, pwm generator) are disabled. therefore, the peripheral can no longer detect events and the preload registers do not operate. when clocks are disabled, write accesses are al- lowed, so for example, mtim counter register can be reset by software. table 56. output configuration summary note 1 : ? peripheral frozen ? configuration is not recommended, as the peripheral may be stopped in a unknown state (depending on pwm generator outputs,etc.). it is better practice to exit from run mode by first setting output state (by toggling ei- ther moe or dac bits) and then to disabling the clock if needed. note 2 : in direct access mode (dac=1), when cke=0 (peripheral clock disabled) only logical level can be applied on the mcox outputs when they are enabled whereas when cke=1 (peripher- al clock enabled), a pwm signal can be applied on them. refer to table 75, ? deadtime generator set-up, ? on page 217 note 3: when clocks are disabled (cke bit reset) while outputs are enabled (moe bit set), the ef- fects on the mcox outputs where pwm signal is applied depend on the running mode selected: ? in voltage mode (voc1 bit=0), the mcox out- puts where pwm signal is applied stay at level 1. ? in current mode (voc1 bit=1), the mcox outputs where pwm signal is applied are put to level 0. in all cases, mcox outputs where a level 1 was applied before disabling the clocks stay at level 1. that is why it is recommended to disable the mcox outputs (reset moe bit) before disabling the clocks. this will put all the mcox outputs under re- set state defined by the corresponding option bit. 76543210 moe cke sr dac v0c1 swa pz dcb moe bit mco[5:0] output pin state 0 reset state 1 output enabled cke bit moe bit dac bit peripheral clock effect on mcox output 0 0 x disabled reset state 0 1 0 disabled peripheral frozen (see note 1 below) 0 1 1 disabled direct access via mphst (only logical level) 1 0 x enabled reset state 1 1 0 enabled standard running mode. 1 1 1 enabled direct access via mphst (pwm can be applied) 1 ST7MC1/st7mc2 207/294 motor controller (cont ? d) effect on pwm generator : the pwm generator 12-bit counter is reset as soon as cke = 0; this en- sures that the pwm signals start properly in all cases. when these bits are set, all registers with preload on update event are transferred to active registers. bit 5 = sr : sensor on/off. 0: sensorless mode 1: position sensor mode table 57. sensor mode selection see also table 62 and table 63 bit 4 = dac : direct access to phase state register. 0: no direct access (reset value). in this mode the preload value of the mphst and mcrb regis- ters is taken into account at the c event. 1: direct access enabled. in this mode, write a val- ue in the mphst register to access the outputs directly. note: in direct access mode (dac bit is set in mcra register), a c event is generated as soon as there is a write access to the oo[5:0] bits in mphst register. in this case, the pwm low/high selection is done by the os0 bit in the mcrb register. table 58. dac bit meaning bit 3 = v0c1 : voltage/current mode 0: voltage mode 1: current mode bit 2 = swa : switched/autoswitched mode 0: switched mode 1: autoswitched mode table 59. switched and autoswitched modes bit 1 = pz : protection from parasitic zero-crossing event detection 0: protection disabled 1: protection enabled note: if the pz bit is set, the z event filter (zef[3:0] in the mzfr register is ignored. bit 0 = dcb : data capture bit 0: use mzprv (z n -1) for multiplication 1: use mzreg (z n ) for multiplication table 60. multiplier result sr bit mode os[2:0] bits behaviour of the output pwm 0 sensors not used os[2:0] bits enabled ? between c n &d ? behaviour, ? between d&z ? behaviour and ? between z&c n+1 ? be- haviour 1 sensors used os1 disabled ? between c n &z ? behaviour and ? between z&c n+1 ? be- haviour moe bit dac bit effect on output 0x reset state depending on the option bit 10 standard running mode. 11 mphst register value (depending on mpol, mpar register values and pwm setting) see table 75 swa bit commutation type mcomp register access 0 switched mode read/write 1 autoswitched mode read/write dcb bit commutation delay 0 mcomp = mwght x mzprv / 256 1 mcomp = mwght x mzreg / 256 1 ST7MC1/st7mc2 208/294 motor controller (cont ? d) control register b (mcrb) read/write reset value: 0000 0000 (00h) bit 7= reserved, must be kept at reset value. bit 6= cpb* : compare bit for zero-crossing detec- tion. 0: zero crossing detection on falling edge 1: zero crossing detection on rising edge bit 5= hdm* : hardware demagnetization event mask bit 0: hardware demagnetization disabled 1: hardware demagnetization enabled bit 4= sdm* : simulated demagnetization event mask bit 0: simulated demagnetization disabled 1: simulated demagnetization enabled bit 3 = ocv : over current handling in voltage mode 0: over current protection is off 1:over current protection is on this bit acts as follows table 61. over current handling bits 2:0 = os2*, os[1:0] : operating output mode selection bits refer to the step behaviour diagrams ( figure 107 , figure 108 ) and table 62, ? step behaviour/ sen- sorless mode, ? on page 208. these bits are used to define the various pwm output configurations. note : os2 is the only preload bit. table 62. step behaviour/ sensorless mode note: for more details, see step behaviour dia- grams ( figure 107 and figure 108 ). * preload bits, new value taken into account at the next c event. a c event is generated at each write to mphst in direct access mode. 76543210 0 cpb* hdm* sdm* ocv os2* os1 os0 clim bit cli bit ocv bit output effect interrupt 00x normal running mode no 01x pwm is put off as current loop effect no 10x normal running mode no 110 pwm is put off as current loop effect yes 111 all mcox outputs are put in reset state (moe reset) yes os2 bit pwm after c and before d os1 bit pwm after d and before z os0 pwm after z and before next c 0 on high channels 0 on high channels 0 on high channels 1 on low channels 1 on low channels 0 on high channels 1 on low channels 1 on low channels 0 on high channels 0 on high channels 1 on low channels 1 on low channels 0 on high channels 1 on low channels 1 ST7MC1/st7mc2 209/294 motor controller (cont ? d) table 63. pwm mode when sr=1 table 64. pwm mode when dac=1 warning: as the mcrb register contains preload bits with, it has to be written as a complete byte. a bit set or bit reset instruction on a non-preload bit will have the effect of resetting all the preload bits. control register c (mcrc) read/write (except edir bit) reset value: 0000 0000 (00h) bit 7= sei/oi : speed error interrupt flag / mtim overflow flag position sensor or sensorless mode (tes[1:0] bits =00) : oi: mtim overflow flag this flag signals an overflow of the mtim timer. it has to be cleared by software. 0: no mtim timer overflow 1: mtim timer overflow note: no interrupt is associated with this flag speed sensor mode (tes[1:0] bits =01, 10, 11) : sei : speed error interrupt flag 0: no tacho error interrupt pending 1: tacho error interrupt pending bit 6= edir/hz : encoder direction bit/ hardware zero-crossing event bit position sensor or sensorless mode (tes[1:0] bits =00) : hz: hardware zero-crossing event bit this read/write bit selects if the z event is hard- ware or not. 0: no hardware zero-crossing event 1: hardware zero-crossing event speed sensor mode (tes[1:0] bits =01, 10, 11) : edir : encoder direction bit this bit is read only. as the rotation direction de- pends on encoder outputs and motor phase con- nections, this bit cannot indicate absolute direc- tion. it therefore gives the relative phase-shift (i.e. advance/delay) between the two signals in quad- rature output by the encoder (see figure 88 ). 0: mcia input delayed compared to mcib input. 1: mcia input in advance compared to mcib input bit 5 = sz : simulated zero-crossing event bit 0: no simulated zero-crossing event 1: simulated zero-crossing event bit 4 = sc : simulated commutation event bit 0: hardware commutation event in auto-switched mode (swa = 1 in mcra register) 1: simulated commutation event in auto-switched mode (swa = 1 in mcra register). bit 3 = splg : sampling z event at high frequency in sensorless mode (sr=0) this bit enables sampling at high frequency in sen- sorless mode independently of the pwm signal or only during on time if the ds[3:0] bits in the mconf register contain a value. refer to table 78, ? sampling delay, ? on page 220 0: normal mode (z sampling at pwm frequency at the end of the off time) 1: z event sampled at f scf (see table 83 ) note: when the splg bit is set, there is no mini- mum off time programmed by the ot [3:0] bits, the off time is forced to 0s. this means that in current mode, the off time of the pwm signal will come only from the current loop. os2 bit pwm after c and before z os1 bit unused os0 pwm after z and before next c 0 on high channels xx 0 on high channels 1 on low channels 1 on low channels xx 0 on high channels 1 on low channels os2 bit unused os1 bit unused os0 pwm on outputs xxxx 0 on high channels 1 on low channels 76 543210 sei / oi edir/ hz sz sc splg vr2 vr1 vr0 1 ST7MC1/st7mc2 210/294 motor controller (cont ? d) bits 2:0 = vr[2:0] : bemf/demagnetisation refer- ence threshold these bits select the vref value as shown in the table 65 . the vref value is used for bemf and demagnetisation detection. table 65. threshold voltage setting *typical values for v dd =5v phase state register (mphst) read/write reset value: 0000 0000 (00h) bit 7:6 = is[1:0]* : input selection bits these bits mainly select the input to connect to comparator as shown in table 66 . the fourth con- figuration (is[1:0] = 11) specifies that an incremen- tal encoder is used (in that case mcia and mcib digital signals are directly connected to the incre- mental encoder interface and the analog multi- plexer is bypassed. table 66. input channel selection bits 5:0 = oo[5:0] *: channel on/off bits these bits are used to switch channels on/off at the next c event if the dac bit =0 or directly if dac=1 0: channel off, the relevant switch is off, no pwm possible 1: channel on the relevant switch is on, pwm is possible (not signifiant when pcn bit is set). table 67. oo[5:0] bit meaning * preload bits, new value taken into account at next c event. caution: as the mphst register contains bits with preload, the whole register has to be written at once. this means that a bit set or bit reset in- struction on only one bit without preload will have the effect of resetting all the bits with preload. vr2 vr1 vr0 vref voltage threshold 111 threshold voltage set by external mcvref pin 110 3.5v* 101 2.5v* 100 2v* 011 1.5v* 010 1v* 001 0.6v* 000 0.2v* 76543210 is1* is0* oo5* oo4* oo3* oo2* oo1* oo0* is1 is0 channel selected 00 mcia 01 mcib 10 mcic 1 1 both mcia and mcib: encoder mode oo[5:0] output channel state 0 inactive 1active 1 ST7MC1/st7mc2 211/294 motor controller (cont ? d) motor current feedback register (mcfr) read/write reset value: 0000 0000 (00h) bit 7= rpgs: register page selection: 0: access to registers mapped in page 0 1: access to registers mapped in page 1 bit 6= rst : reset mtc registers. software can set this bit to reset all mtc registers without resetting the st7. 0: no mtc register reset 1: reset all mtc registers bits 5:3 = cff[2:0] : current feedback filter bits these bits select the number of consecutive valid samples (when the current is above the limit) needed to generate the active event. sampling is done at f periph /4. table 68. current feedback filter setting bits 2:0 = cfw[2:0] : current window filter bits: these bits select the length of the blanking win- dow activated each time pwm is turned on. the filter blanks the output of the current comparator. table 69. current feedback window setting note: times are indicated for 4 mhz f periph 76543210 rpgs rst cff2 cff1 cff1 cfw2 cfw1 cfw0 cff2 cff1 cff0 current feedback samples 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 cfw2 cfw1 cfw0 blanking window 0 0 0 blanking window off 001 0.5s 010 1s 011 1.5s 100 2s 101 2.5s 110 3s 111 3.5s 1 ST7MC1/st7mc2 212/294 motor controller (cont ? d) motor d event filter register (mdfr) read/write reset value: 0000 1111 (0fh) bits 7:4 = def[3:0] : d event filter bits these bits select the number of valid consecutive d events (when the d event is detected) needed to generate the active event. sampling is done at the selected f scf frequency, see table 83 . table 70. d event filter setting bit 3:0 = dwf[3:0] : d window filter bits these bits select the length of the blanking win- dow activated at each c event. the filter blanks the d event detection. table 71. d window filter setting note: times are indicated for 4 mhz f periph 76543210 def3 def2 def1 def0 dwf3 dwf2 dwf1 dwf0 def3 def2 def1 def0 d event samples sr=1 0000 1 no d event filter 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 dwf3 dwf2 dwf1 dwf0 c to d window filter in sensorless mode (sr=0) sr=1 0000 5s no window filter after c event 0001 10s 0010 15s 0011 20s 0100 25s 0101 30s 0110 35s 0111 40s 1000 60s 1001 80s 1010 100s 1011 120s 1100 140s 1101 160s 1110 180s 1111 200s ST7MC1/st7mc2 213/294 motor controller (cont ? d) reference register (mref) read/write reset value: 0000 0000 (00h) bit 7 = hst : hysteresis comparator value. this read only bit contains the hysteresis compa- rator output. 0: demagnetisation/bemf comparator is under v ref 1: demagnetisation/bemf comparator is above v ref bit 6 = cl : current loop comparator value. this read only bit contains the current loop compa- rator output value. 0: current detect voltage is under v cref 1: current detect voltage is above v cref bit 5= cfav : current feedback amplifier entry validation 0: oaz is the current comparator entry 1: mccfi is the current comparator entry bits 4:3 = hfe[1:0] : chopping mode selection these bits select the chopping mode as shown in the following table. table 72. chopping mode bits 2:0 = hfrq[2:0] : chopper frequency selec- tion these bits select the chopping frequency. table 73. chopping frequency selection note: the chopper signal has a 50% duty cycle. 76543 2 1 0 hst cl cfav hfe1 hfe0 hfrq2 hfrq1 hfrq0 hfe1 hfe0 chopping mode 00 off 0 1 on low channels only 1 0 on high channels only 1 1 both high and low channels hfrq2 hfrq1 hfrq0 chopping frequency f mtc = 16mhz f mtc = 8mhz chopping frequency f mtc = 4mhz 0 0 0 100 khz 50 khz 0 0 1 200 khz 100 khz 0 1 0 400 khz 200 khz 0 1 1 500 khz 250 khz 1 0 0 800 khz 400 khz 1011 mhz500 khz 1 1 0 1.33 mhz 666.66 mhz 1 1 1 2 mhz 1 mhz ST7MC1/st7mc2 214/294 motor controller (cont ? d) pwm control register (mpcr) read/write reset value: 0000 0000 (00h) bit 7 = pms: pwm mode selection . 0: standard mode: bit b7 in the mcpxh register represents the extension bit. 1: ? 8-bit ? mode: bit b7 (extension bit) in the mcpxh register is located in the mpcr register (ovfx bits); the number of active bits in mcpxh and mcpxl is decreased to b15:b8 instead of b15:b3. bit 6 = ovfu: phase u 100% duty cycle selec- tion. 0: duty cycle defined by mcpuh:mcpul register. 1: duty cycle set at 100% on phase u at next up- date event and maintained till the next one. this bit is reset once transferred to the active register on update event. bit 5 = ovfv: phase v 100% duty cycle selection. 0: duty cycle defined by mcpvh:mcpvl register. 1: duty cycle set at 100% on phase v at next up- date event and maintained till the next one. this bit is reset once transferred to the active register on update event. bit 4 = ovfw: phase w 100% duty cycle selec- tion. 0: duty cycle defined by mcpwh:mcpwl regis- ter. 1: duty cycle set at 100% on phase w at next up- date event and maintained till the next one. this bit is reset once transferred to the active register on update event. bit 3 = cms: pwm counter mode selection. 0: edge-aligned mode 1: center-aligned mode bits 2:0 = pcp[2:0] pwm counter prescaler value . this value divides the f mtc frequency by n, where n is pcp[2:0] value. table 74 shows the resulting frequency of the pwm counter input clock. table 74. pwm clock prescaler 70 pms ovfu ovfv ovfw cms pcp2 pcp1 pcp0 pcp2 pcp1 pcp0 pwm counter input clock 000 f mtc 001 f mtc /2 010 f mtc /3 011 f mtc /4 100 f mtc /5 101 f mtc /6 110 f mtc /7 111 f mtc /8 ST7MC1/st7mc2 215/294 motor controller (cont ? d) repetition counter register (mrep) read/write reset value: 0000 0000 (00h) bits 7:0 = rep[7:0] repetition counter value (n). this register allows the user to set-up the update rate of the pwm counter compare register (i.e. pe- riodic transfers from preload to active registers), as well as the pwm update interrupt generation rate, if these interrupts are enabled. each time the mrep related down-counter reaches zero, the compare registers are updated, a u interrupt is generated and it re-starts counting from the mrep value. after a microcontroller reset, setting the cke bit in the mcra register (i.e. enabling the clock for the mtc peripheral) forces the transfer from the mrep preload register to its active register and generates a u interrupt. during run-time (while cke bit = 1) a new value entered in the mrep preload register is taken into account after a u event. as shown in figure 120 , (n+1) value corresponds to: ? the number of pwm periods in edge-aligned mode ? the number of half pwm periods in center- aligned mode. ? compare phase w preload register high (mcpwh) read/write reset value: 0000 0000 (00h) bits 7:0 = cpwh[7:0] most significant byte of phase w preload value compare phase w preload register low (mcpwl) read/write (except bits 2:0) reset value: 0000 0000 (00h) bits 7:5 = cpwl[7:3] low bits of phase w preload value . bits 2:0 = reserved. compare phase v preload register high (mcpvh) read/write reset value: 0000 0000 (00h) bit 7:0 = cpvh[7:0] most significant byte of phase v preload value compare phase v preload register low (mcpvl) read/write (except bits 2:0) reset value: 0000 0000 (00h) bits 7:5 = cpvl[7:3] low bits of phase v preload value . bits 2:0 = reserved. 70 rep7 rep6 rep5 rep4 rep3 rep2 rep1 rep0 70 cpwh 7 cpwh 6 cpwh 5 cpwh 4 cpwh 3 cpwh 2 cpwh 1 cpwh 0 70 cpwl 7 cpwl 6 cpwl 5 cpwl 4 cpwl 3 --- 70 cpvh7 cpvh6 cpvh5 cpvh4 cpvh3 cpvh2 cpvh1 cpvh0 70 cpvl7 cpvl6 cpvl5 cpvl4 cpvl3 - - - ST7MC1/st7mc2 216/294 motor controller (cont ? d) compare phase u preload register high (mcpuh) read/write reset value: 0000 0000 (00h) bits 7:0 = cpuh[7:0] most significant byte of phase u preload value compare phase u preload register low (mcpul) read/write read/write (except bits 2:0) reset value: 0000 0000 (00h) bits 7:5 = cpul[7:3] low bits of phase u preload value . bits 2:0 = reserved. compare 0 preload register high (mcp0h) read/write (except bits 7:4) reset value: 0000 1111 (0fh) bits 7:4 = reserved. bits 3:0 = cp0h[3:0] most significant bits of com- pare 0 preload value. compare 0 preload register low (mcp0l) read/write reset value: 1111 1111 (ffh) bits 7:0 = cp0l[7:0] low byte of compare 0 preload value . note 1 : the 16-bit compare registers mcmpox, mcmpux, mcmpvx, mcmpwx msb and lsb parts have to be written sequentially before being taken into account when an update event occurs; refer to section 9.6.10.4 on page 197 for details. note 2: the cpb, hdm, sdm, os2 bits in the mcrb and the bits oe[5:0] are marked with *. it means that these bits are taken into account at the following commutation event (in normal mode) or when a value is written in the mphst register when in direct access mode. for more details, re- fer to the description of the dac bit in the mcra register. the use of a preload register allows all the registers to be updated at the same time. warning: access to preload registers special care has to be taken with preload regis- ters, especially when using the st7 bset and bres instructions on mtc registers. for instance, while writing to the mphst register, you will write the value in the preload register. however, while reading at the same address, you will get the current value in the register and not the value of the preload register. excepted for three-phase pwm generator ? s regis- ters, all preload registers are loaded in the active registers at the same time. in normal mode this is done automatically when a c event occurs, how- ever in direct access mode (dac bit=1) the preload registers are loaded as soon as a value is written in the mphst register. caution: access to write-once bits special care has to be taken with write-once bits in mpol and mdtg registers; these bits have to be accessed first during the set-up. any access to the other bits (not write-once) through a bres or a bset instruction will lock the content of write-once bits (no possibility for the core do distinguish indi- vidual bit access: read/write internal signal acts on a whole register only). this protection is then only unlocked after a processor hardware reset. 70 cpuh 7 cpuh 6 cpuh 5 cpuh 4 cpuh 3 cpuh 2 cpuh 1 cpuh 0 70 cpul7 cpul6 cpul5 cpul4 cpul3 - - - 70 ----cp0h3cp0h2cp0h1cp0h0 70 cp0l7 cp0l6 cp0l5 cp0l4 cp0l3 cp0l2 cp0l1 cp0l0 ST7MC1/st7mc2 217/294 motor controller (cont ? d) dead time generator register (mdtg) read/write (except bits 5:0 write once-only) reset value: 1111 1111 (ffh) bit 7 = pcn: number of pwm channels . 0: only pwm u signal is output to the pwm man- ager for six-step mode motor control (e.g. pm bldc motors) 1: the three pwm signals u, v and w are output to the channel manager (e.g. for three-phase sinewave generation) bit 6 = dte* : dead time generator enable 0: disable the dead time generator 1: enable the dead time generator and apply complementary pwm signal to the adjacent switch * write once-only bit if pcn bit is set, read/write if pcn bit is reset. to clear the dte bit if pcn=1, it is mandatory to clear the pcn bit first. table 75. deadtime generator set-up note 1: this table is true on condition that the cke bit is set (peripheral clock enabled) and the moe bit is set (mcox outputs enabled). see table 56, ? output configuration summary, ? on page 206 when the pcn bit is reset (e.g. for pm bldc mo- tors), in direct access mode (dac=1), if the dte bit is reset, pwm signals can be applied on the mcox outputs but not complementary pwm. of course, logical levels can be also applied on the outputs. if the dte bit is set (pcn=0 and dac=1), chan- nels are paired and complementary pwm signals can be output on the mcox pins. this will follow the rules detailed in table 53, ? dead time genera- tor outputs, ? on page 193 as the channels are grouped in pairs. in this case, the pwm application is selected by the os0 bit in the mcrb register. it is also possible to add a chopper on the pwm signal output using bits hfe[1:0] and hfrq[2:0] in the mref register. caution 1 : the pwm mode will be selected via the 00[5:0] bits in the mphst register, the oe[5:0] bits in the mpar register and the os2 and os0 bits in the mcrb register as shown in table 63, ? pwm mode when sr=1, ? on page 209. caution 2 : when driving motors with three inde- pendent pairs of complementary pwm signals (pcn=1), disabling the deadtime generator (dte=0) causes the deadtime to be null: high and low side signals are exactly complemented. it is therefore recommended not to disable the deadtime generator (it may damage the power stage), unless deadtimes are inserted externally. bits 5:0 = dtg[5:0]* dead time generator set-up . these bits set-up the deadtime duration and reso- lution. refer to table 52, ? dead time programming and example, ? on page 191 for details. with f mtc = 16mhz dead time values range from 125ns to 16s with steps of 125ns, 250ns and 500ns. * write-once bits; once write-accessed these bits cannot be re-written unless the processor is reset (see ? caution: access to write-once bits ? on page 216.). 70 pcn dte dtg5 dtg4 dtg3 dtg2 dtg1 dtg0 dac pcn bit in mdtg register dte bit in mdtg register complementary pwm applied to adjacent switch 00 0 no 0 0 1 yes 0 1 1 yes 01 0 yes, but without deadtime 10 0 no complementary pwm 1 0 1 yes 1 1 1 yes 11 0 yes, but without deadtime ST7MC1/st7mc2 218/294 motor controller (cont ? d) polarity register (mpol) read/write (some bits write-once) reset value: 0011 1111 (3fh) bit 7 = zvd : z vs d edge polarity. 0: zero-crossing and end of demagnetisation have opposite edges 1: zero-crossing and end of demagnetisation have same edge bit 6 = reo : read on high or low channel bit 0: read the bemf signal on high channels 1: read on low channels note: this bit always has to be configured whatev- er the sampling method. bits 5:0 = op[5:0] *: output channel polarity. these bits are used together with the oo [5:0] bits in the mphst register to control the output chan- nels. 0: output channel is active low 1: output channel is active high. * write-once bits; once write-accessed these bits cannot be re-written unless the processor is reset (see ? caution: access to write-once bits ? on page 216.). table 76. output channel state control warning: op[5:0] bits in the mpol register must be configured as required by the application be- fore enabling the mco[5:0] outputs with the moe bit in the mcra register. 76543210 zvd reo op5 op4 op3 op2 op1 op0 op[5:0] bit oo[5:0] bit mco[5:0] pin 0 0 1 (off) 0 1 0 (pwm possible) 1 0 0 (off) 1 1 1 (pwm possible) ST7MC1/st7mc2 219/294 motor controller (cont ? d) pwm register (mpwme) read/write reset value: 0000 0000 (00h) bit 7 = dg : debug option. this bit is used to enter debug mode. as a result, c, d and z events are output on 2 pins mcdem and mczem in switched and autoswitched mode, c and u events are output in speed measurement mode. refer to section 9.6.7.3 on page 168 for more details 0: normal mode 1: debug mode bit 6 = pwmw : pwm w output control 0: pwm on compare register w is not output on mcpwmw pin 1: pwm on compare register w is output on mcpwmw pin bit 5 = pwmv : pwm v output control 0: pwm on compare register v is not output on mcpwmv pin 1: pwm on compare register v is output on mcp- wmv pin bit 4 = pwmu : pwm u output control 0: pwm on compare register u is not output on mcpwmu pin 1: pwm on compare register u is output on mcpwmu pin bits 3:0 = ot[3:0] : off time selection these bits are used to select the off time in sen- sorless current mode as shown in the following ta- ble. table 77. off time bits note: times are indicated for 4 mhz f periph 76543210 dg pwmw pwmv pwmu ot3 ot2 ot1 ot0 ot3 ot2 ot1 ot0 off time sen- sorless mode (sr=0) (ds[3:0]=0) sensor mode (sr=1) or sam- pling during on ime in sensor- less (splg =1 and/or ds [3:0] bits) 0000 2.5 s no minimum off - time 0001 5 s 0010 7.5 s 0011 10 s 0 1 0 0 12.5 s 0101 15 s 0 1 1 0 17.5 s 0111 20 s 1 0 0 0 22.5 s 1001 25 s 1 0 1 0 27.5 s 1011 30 s 1 1 0 0 32.5 s 1101 35 s 1 1 1 0 37.5 s 1111 40 s ST7MC1/st7mc2 220/294 motor controller (cont ? d) configuration register (mconf) read/write reset value: 0000 0010 (02h) bits 7:4 = ds[3:0] : delay for sampling at ton these bits are used to define the delay inserted before sampling in order to sample during pwm on time. table 78. sampling delay note: times are indicated for 4 mhz f periph bit 3 = soi sampling out interrupt flag. this interrupt indicates that the sampling that should have been done during ton has occured during the next toff. in this case, the sample is dis- carded. 0: no sampling out interrupt pending 1: sampling out interrupt pending bit 2 = som: sampling out mask bit. this interrupt is available only for z event sampling as d event sampling is always done at f scf high frequency. 0: sampling out interrupt disabled 1: sampling out interrupt enabled this interrupt is available only when a delay has been set in the ds[3:0] bits in the mconf register. note: it is recommended to disable the sampling out interrupt when software z event is enabled (sz bit in mcrc register is set) and if the value in the ds[3:0] bits is modified to change the sampling method during the application. bits [1:0] = xt16:xt8 bldc drive motor control peripheral input frequency selection: table 79. peripheral frequency caution: it is recommended to set the peripheral frequency to 4mhz. setting f periph =f mtc is used mainly when f osc2 = 4mhz (for low power con- sumption). 76543210 ds3 ds2 ds1 ds0 soi som xt16 xt8 ds3 ds2 ds1 ds0 delay added to sample at ton 0 0 0 0 no delay added. sample during toff 0 0 0 1 2.5 s 0010 5 s 0 0 1 1 7.5 s 0100 10 s 0 1 0 1 12.5 s 0110 15 s 0 1 1 1 17.5 s 1000 20 s 1 0 0 1 22.5 s 1010 25 s 1 0 1 1 27.5 s 1100 30 s 1 1 0 1 32.5 s 1110 35 s 1 1 1 1 37.5 s xt16 xt8 peripheral frequency 00 f periph = f mtc 01 f periph = f mtc /2 10 f periph = f mtc /4 11 f periph = f mtc /4 (same as xt16=1,xt8=0) ST7MC1/st7mc2 221/294 motor controller (cont ? d) parity register (mpar) read/write reset value: 0000 0000 (00h) bits 7:6 = tes[1:0] : tacho edge selection bits the primary function of these bits is to select the edge sensitivity of the tachogenerator capture log- ic; clearing both tes[1:0] bits specifies that the in- put detection block does not operate in speed sensor mode but either in position sensor or sen- sorless mode for a six-step motor drive). bits 5:0 = oe[5:0] : output parity mode. 0: output channel is high 1: output channel low note : these bits are not significant when pcn=1 (configuration with three independent phases). 76543210 tes1 tes0 oe5 oe4 oe3 oe2 oe1 oe0 tes 1 tes 0 edge sensitivity operating mode 0 0 not applicable position sensor or sensorless 0 1 rising edge speed sensor 1 0 falling edge speed sensor 11 rising and falling edges speed sensor ST7MC1/st7mc2 222/294 motor controller (cont ? d) motor z event filter register (mzfr) read/write reset value: 0000 1111 (0fh) bits 7:4 = zef[3:0] : z event filter bits these bits select the number of valid consecutive z events (when the z event is detected) needed to generate the active event. sampling is done at the selected f scf frequency (see table 83 .) or at pwm frequency. table 81. z event filter setting bits 3:0 = zwf[3:0] : z window filter bits these bits select the length of the blanking win- dow activated at each d event. the filter blanks the z event detection until the end of the time win- dow. table 82. z window filter setting note: times are indicated for 4 mhz f periph 76543210 zef3 zef2 zef1 zef0 zwf3 zwf2 zwf1 zwf0 zef3 zef2 zef1 zef0 z event samples 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16 zwf3 zwf2 zwf1 zwf0 d to z window fil- ter in sensorless mode (sr=0) sr=1 0000 5 s no win- dow filter after d event 0001 10 s 0010 15 s 0011 20 s 0100 25 s 0101 30 s 0110 35 s 0111 40 s 1000 60 s 1001 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s ST7MC1/st7mc2 223/294 motor controller (cont ? d) motor sampling clock register (mscr) read/write reset value: 0000 0000 (00h) bit 7 = zsv z event sampling validation when moe bit is reset this bit enables/disables z event sampling in ei- ther mode (sampling at pwm frequency or at f scf frequency selected by scf[1:0] bits) 0: z event sampling disabled 1: z event sampling enabled bits 6:4 = reserved, must be kept cleared. bits 3:2 = scf[1:0] sampling clock frequency these bits select the sampling clock frequency (f scf ) used to count d & z events. table 83. sampling clock frequency note: times are indicated for 4 mhz f periph bit 1 = ecm : encoder capture mode this bit is used to select the source of events which trigger the capture of the [mtim:mtiml] counter when using encoder speed sensor (see figure 88 ). 0: real time clock interrupts 1: read access on mtim register bit 0 = diss data input selection this setting is effective only if pcn=0, tes=00 and sr=0. 0: unused mcix inputs are grounded 1: unused mcix inputs are put in hiz 76543210 zsv 0 0 0 scf1 scf0 ecm diss scf1 scf0 f scf 0 0 1 mhz (every 1s) 0 1 500 khz (every 2s) 1 0 250 khz (every 4s) 1 1 125 khz (every 8s) ST7MC1/st7mc2 224/294 figure 121. detailed view of the mtc for pm bldc motor control mtim [8-bit up counter] c a b hv d q cp microcontroller + v ref - mpol reg moe bit mccfi mco0 mco2 mco4 mco1 mco3 mco5 is n bit board + motor cff[2:0] bit vr2-0 z h mcic mcia mcib d h mwght reg [a n+1 ] mzreg reg [z n ] a x b / 256 f mtc mzprv reg [z n-1 ] c s,h d s st3-0 bits 4 dcb bit sdm n bit swa bit mdreg reg [d n ] compare compare mcomp reg [c n+1 ] z h 1 / 2 ratio 1 / 2 mzreg mtim z s,h sa3-0 & 12-bit pwm generator sq r v i d h nmces +1 -1 z clr x6 x6 ck misr reg c s,h d s,h z s,h e mpar reg 6 6 8 8 8 8 1 1 ? 1/128 ot1-0 bits n n-1 r + r - r -/+ mimr reg cl 3 mphst n reg sr bit + - c ext d s,h 1 2 v i 1 2 1 /20 1 / 4 c s,h d s,h a os n c s,h d s,h < 55h? = ffh? filter / c 1 0 swa bit c h (v) r 1ext r 2ext v dd (i) compare u mcpwmu mcpwmv mcpwmw mcvref splg dwf[3:0] sz n compare filter / d zwf[3:0] bit z s ch0 ch1 ch2 ch3 ch4 ch5 bits pcn bit =0 mdtg register 8 2 6 dead time dead time dead time high frequency chopper oap oan mccref mcpwmu/v/w oaon + - mpwme reg mref reg cli xt16:xt8 bit oaz cfav bit drivers clim bit cli bit ocv bit f periph prescaler d/z window filter z event generation d event generation cfw[2:0] bit ST7MC1/st7mc2 225/294 figure 122. detailed view of the mtc configured for induction motor control (proposal) c a b hv microcontroller mpol reg moe bit mccfi mco0 mco2 mco4 mco1 mco3 mco5 is n bit board + motor mcic mcia mcib f mtc nmces x6 x6 misr reg c u s e mpar reg 6 1 r -/+ mimr reg cl + - pcn bit =1 mdtg register 8 2 6 dead time dead time dead time high frequency chopper oap oan mccref oaon + - mref reg cl oaz cfav bit s compare clock msbits clr c c mtim mtiml mzreg mzprv lsbits c mdreg up to 16mhz st[3:0] bits 4 1 / 2 rati o mzreg < 55h? mtim = ffh? +1 -1 r + r - is[1:0] bits tes[1:0] bits is[1:0] bits tes[1:0] bits ecm bit c mtim read rtc interrupt compare ffh (fixed) encoder clock encoder interface direction or or edir bit tacho capture tes bits clock ratio mcia mcib mcia or mcib or mcic tachogenerator incremental encoder t e three-phase induction motor 12-bit compare 0 register 12-bit pwm counter 13-bit compare w register up to 16mhz phase w 13-bit compare u register phase u 13-bit compare v register phase v u u u u clear or pcp[2:0] bits repetition counter u mpcr register up/down mrep reg pwm clock f mtc e drivers 16-bit capture register 16-bit up counter u ST7MC1/st7mc2 226/294 motor controller (cont ? d) table 84. mtc page 0 register map and reset values register name 765 4 3210 mtim reset value t7 0 t6 0 t5 0 t4 0 t3 0 t2 0 t1 0 t0 0 mtiml reset value tl7 0 tl6 0 tl5 0 tl4 0 tl3 0 tl2 0 tl1 0 tl0 0 mzprv reset value zp7 0 zp6 0 zp5 0 zp4 0 zp3 0 zp2 0 zp1 0 zp0 0 mzreg reset value zc7 0 zc6 0 zc5 0 zc4 0 zc3 0 zc2 0 zc1 0 zc0 0 mcomp reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 mdreg reset value dn7 0 dn6 0 dn5 0 dn4 0 dn3 0 dn2 0 dn1 0 dn0 0 mwght reset value an7 0 an6 0 an5 0 an4 0 an3 0 an2 0 an1 0 an0 0 mprsr reset value sa3 0 sa2 0 sa1 0 sa0 0 st3 0 st2 0 st1 0 st0 0 mimr reset value pum 0 sem 0 rim 0 clim 0 eim 0 zim 0 dim 0 cim 0 misr reset value pui 0 rpi 0 rmi 0 cli 0 ei 0 zi 0 di 0 ci 0 mcra reset value moe 0 cke 0 sr 0 dac 0 v0c1 0 swa 0 pz 0 dcb 0 mcrb reset value 0 cpb 0 hdm 0 sdm 0 ocv 0 os2 0 os1 0 os0 0 mcrc reset value sei / oi 0 edir / hz 0 sz 0 sc 0 splg 0 vr2 0 vr1 0 vr0 0 mphst reset value is1 0 is0 0 oo5 0 oo4 0 oo3 0 oo2 0 oo1 0 oo0 0 mdfr reset value def3 0 def2 0 def1 0 def0 0 dwf3 1 dwf2 1 dwf1 1 dwf0 1 mcfr reset value rpgs 0 rst 0 cff2 0 cff1 0 cff0 0 cfw2 0 cfw1 0 cfw0 0 mref reset value hst 0 cl 0 cfav 0 hfe1 0 hfe0 0 hfrq2 0 hfrq1 0 hfrq0 0 mpcr reset value pms 0 ovfu 0 ovfv 0 ovfw 0 cms 0 pcp2 0 pcp1 0 pcp0 0 mrep reset value rep7 0 rep6 0 rep5 0 rep4 0 rep3 0 rep2 0 rep1 0 rep0 0 mcpwh reset value cpwh7 0 cpwh6 0 cpwh5 0 cpwh4 0 cpwh3 0 cpwh2 0 cpwh1 0 cpwh0 0 ST7MC1/st7mc2 227/294 table 85. mtc page 1 register map and reset values mcpwl reset value cpwl7 0 cpwl6 0 cpwl5 0 cpwl4 0 cpwl3 0 000 mcpvh reset value cpvh7 0 cpvh6 0 cpvh5 0 cpvh4 0 cpvh3 0 cpvh2 0 cpvh1 0 cpvh0 0 mcpvl reset value cpvl7 0 cpvl6 0 cpvl5 0 cpvl4 0 cpvl3 0 000 mcpuh reset value cpuh7 0 cpuh6 0 cpuh5 0 cpuh4 0 cpuh3 0 cpuh2 0 cpuh1 0 cpuh0 0 mcpul reset value cpul7 0 cpul6 0 cpul5 0 cpul4 0 cpul3 0 000 mcp0h reset value 0000 cp0h3 1 cp0h2 1 cp0h1 1 cp0h0 1 mcp0l reset value cp0l7 1 cp0l6 1 cp0l5 1 cp0l4 1 cp0l3 1 cp0l2 1 cp0l1 1 cp0l0 1 register name 765 4 3210 mdtg reset value pcn 1 dte 1 dtg5 1 dtg4 1 dtg3 1 dtg2 1 dtg1 1 dtg0 1 mpol reset value zvd 0 reo 0 op5 1 op4 1 op3 1 op2 1 op1 1 op0 1 mpwme reset value dg 0 pwmw 0 pwmv 0 pwmu 0 ot3 0 ot2 0 ot1 0 ot0 0 mconf reset value ds3 0 ds2 0 ds1 0 ds0 0 soi 0 som 0 xt16 1 xt8 0 mpar reset value tes1 0 tes0 0 oe5 0 oe4 0 oe3 0 oe2 0 oe1 0 oe0 0 mzfr reset value zef3 0 zef2 0 zef1 0 zef0 0 zwf3 1 zwf2 1 zwf1 1 zwf0 1 mscr reset value zsv 0000 scf1 0 scf0 0 ecm 0 diss 0 register name 765 4 3210 ST7MC1/st7mc2 228/294 figure 123. page mapping for motor control page 0 mtim mtiml mdfr mcfr mzprv mzreg mcomp mdreg mwght mprsr mimr misr mcra mcrb mcrc mphst mref mpcr mrep mcpuh mcpul mcpwh mcpwl mcpvh mcpvl mcpoh mcpol page 1 mdtg mpol mconf mpar rpgs bit =1 in mcfr register mpwme 50 51 52 53 52 54 mzfr 55 mscr 56 ST7MC1/st7mc2 229/294 9.7 operational amplifier (oa) 9.7.1 introduction the st7 op-amp module is designed to cover various types of microcontroller applications where analog signals amplifiers are used. it may be used to perform a variety of functions such as: differential voltage amplifier, comparator/ threshold detector, adc zooming, impedance adaptor, general purpose operational amplifier. 9.7.2 main features this module includes: 1 stand alone op-amp that may be externally connected using i/o pins op-amp output can be internally connected to the adc inputs as well as to the motor control current feedback comparator input input offset compensation with optional average on/off bit to reduce power consumption and to enable the input/output connections with external pins 9.7.3 general description this op-amp can be used with 3 external pins (see device pinout description) and can be inter- nally connected to the adc and the motor control cells. the gain must be fixed with external compo- nents. the input/output pins are connected to the op- amp as soon as it is switched on (through the oacsr register). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ? i/o ports ? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. the output is not connected (hiz) when the op- amp is off. however the pin can still be used as an adc or mtc input in this case. when the op-amp is on the output is connected to a dedicated pin which is not a standard i/o port. the output can be also be connected to the adc or the mtc. the switches are controlled software (refer to the mtc and adc chapters). 9.7.4 input offset compensation the op-amp incorporates a method to minimize the input offset which is dependant on process lot. it is useable by setting the offcmp bit of the con- trol register, which launch the compensation cycle. the cmpvr bit is set by hardware as soon as this cycle is completed. the compensation is valid as long as the offcmp bit is high. it can be re-per- formed by cycling offcmp ? 0 ? then ? 1 ? . the compensation can be improved by averaging the calculation (over 16 times) setting the avgc- mp bit. ST7MC1/st7mc2 230/294 op-amp module (cont ? d) 9.7.5 op-amp programming the flowchart for op-amp operation is shown in figure 124 figure 124. normal op-amp operation. power on reset oacsr = 0000 0000 write oacsr = x0010xx0 wait for amplifier to wake up (t wakeup ) compensation offset ? average compensation ? write oacsr = x101 0xx0 wait for 1536*tcpu cycles read cmpovr = 1 write oacsr = x0p1 pxx0 p : same as before write oacsr = x111 0xx0 wait for 24576*tcpu cycles read cmpovr = 1 need closed loop gain > 20db @ 100khz ? write oacsr = x1p1 1xx0 p : same as before op-amp useable re-compensate offset ? external components always connected no yes yes no yes no no yes #offcmp & avgcmp should be set simultenaously #the highgain bit can also be written in step (1) or (2) (1) (2b) (4) (3) # (2a) ST7MC1/st7mc2 231/294 op-amp module (cont ? d) 9.7.6 low power modes note: the op-amp can be disabled by resetting the oaon bit. this feature allows reduced power consumption when the amplifier is not used. 9.7.7 interrupts none. 9.7.8 register description control/status register (oacsr) read/write (except bit 7 read only) reset value: 0000 0000(00h) bit 7 = cmpovr compensation completed this read-only bit contains the offset compensa- tion status. 0: no offset compensation if offcmp = 0, or offset compensation cycle not completed if offcmp = 1 1: offset compensation completed if offcmp = 1 bit 6 = offcmp offset compensation 0: reset offset compensation values 1: request to start offset compensation bit 5 = avgcmp average compensation 0: one-shot offset compensation 1: average offset compensation over 16 times bit 4 = oaon amplifier on 0: op-amp powered off 1: op-amp on bit 3 = highgain gain range selection this bit must be programmed depending on the application. it can be used to ensure 35db open loop gain when high, it must be low when the closed loop gain is below 20db for stability rea- sons. 0: closed loop gain up to 20db 1: closed loop gain more than 20db bits 2:0 = reserved, must be kept cleared. mode description wait no effect on op-amp halt op-amp disabled after wake-up from halt mode, the op- amp requires a stabilization time (see electrical characteristics) (to be defined) 76543210 cmp ovr off cmp avg cmp oao n high gain 000 ST7MC1/st7mc2 232/294 9.8 10-bit a/d converter (adc) 9.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. 4 of the channels have dedicated circuitry and pins to re- duce noise and leakage so as to improve the accu- racy and reduce the sensitivity to analog source impedance. the result of the conversion is stored in 2 8-bit data registers. the a/d converter is controlled through a control/status register. 9.8.2 main features 10-bit conversion up to 16 channels with multiplexed input 2 software-selectable sample times external positive reference voltage v ref+ can be independent from supply linear successive approximation data registers (dr) which contain the results conversion complete status flag maskable interrupt on/off bit (to reduce consumption) the block diagram is shown in figure 125 . 9.8.3 functional description 9.8.3.1 analog references v ref+ and v ref- are the high and low level refer- ence voltage pins. conversion accuracy may therefore be impacted by voltage drops and noise on these lines. v ref+ can be supplied by an inter- mediate supply between v dda and v ssa to change the conversion voltage range. v ref- must be tied to v ssa . an internal resistor bridge is im- plemented between v ref+ and v ref- pins, with a typical value of 15k ? 9.8.3.2 analog power supply v dda and v ssa are the supply and ground pins providing power to the converter part. they must figure 125. adc block diagram cs2 cs1 eoc prsc1prsc0 adon cs0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrmsb 4 f adc d1 d0 adcdrlsb prescaler 00 0000 cs3 mccbcr it request adcie adsts ST7MC1/st7mc2 233/294 10-bit a/d converter (adc) (cont ? d) 9.8.3.3 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v ref+ (high-level voltage reference) then the conversion result is ffh in the adcdrmsb register and 03h in the adcdrlsb register (without overflow indi- cation). if the input voltage (v ain ) is lower than v ref- (low- level voltage reference) then the conversion result in the adcdrmsb and adcdrlsb registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrmsb and adcdrlsb registers. the accuracy of the con- version is described in the electrical characteris- tics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. r ref is the value of the resistive bridge imple- mented in the device between v ref+ and v ref-. 9.8.3.4 a/d conversion the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ? i/o ports ? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. if the application used the high-im- pedance analog inputs, then the sample time should be stretched by setting the adsts bit in the mccbcr register. in the adccsr register: ? select the cs[3:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: ? set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. ? the eoc bit is kept low by hardware during the conversion. note: changing the a/d channel during conver- sion will stop the current conversion and start con- version of the newly selected channel. ST7MC1/st7mc2 234/294 10-bit a/d converter (adc) (cont ? d) when a conversion is complete: ? the eoc bit is set by hardware ? an interrupt request is generated if the adcie bit in the mccbcr register is set (see section 5.4.7 on page 33 ). ? the result is in the adcdr registers and re- mains valid until the next conversion has end- ed. to read the 10 bits, perform the following steps: 1. poll the eoc bit or wait for eoc interrupt 2. read adcdrlsb 3. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. to read only 8 bits, perform the following steps: 1. poll the eoc bit or wait for eoc interrupt 2. read adcdrmsb the eoc bit is reset by hardware once the ad- cdrmsb is read. changing the conversion channel the application can change channels during con- version. in this case the current conversion is stopped and the a/d converter starts converting the newly selected channel. adccr consistency if an end of conversion event occurs after soft- ware has read the adcdrlsb but before it has read the adcdrmsb, there would be a risk that the two values read would belong to different sam- ples. to guarantee consistency: ? the adcdrmsb and the adcdrlsb are locked when the adccrlsb is read ? the adcdrmsb and the adcdrlsb are un- locked when the msb is read or when adon is reset. thus, it is mandatory to read the adcdrmsb just after reading the adcdrlsb. otherwise the ad- cdr register will not be updated until the ad- cdrmsb is read. 9.8.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed. 9.8.5 interrupts 1) the adcie bit is in the mccbcr register (see section 5.4.7 on page 33 ) mode description wait no effect on a/d converter halt a/d converter disabled. after wake up from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. interrupt event event flag enable control bit exit from wait exit from halt end of conver- sion eoc adcie 1) yes no ST7MC1/st7mc2 235/294 10-bit a/d converter (adc) (cont ? d) 9.8.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrmsb register. 0: conversion is not complete 1: conversion complete bit 6:5 = prsc[1:0] adc clock prescaler selection these bits are set and cleared by software. bit 4 = adon a/d converter on this bit is set and cleared by software. 0: disable adc and stop conversion 1: enable adc and start conversion bit 3:0 = cs[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register (adcdrmsb) read only reset value: 0000 0000 (00h) bit 7:0 = d[9:2] msb of analog converted value this register contains the msb of the converted analog value. data register (adcdrlsb) read only reset value: 0000 0000 (00h) bit 7:2 = reserved. forced by hardware to 0. bit 1:0 = d[1:0] lsb of analog converted value this register contains the lsb of the converted an- alog value. 70 eoc prsc1 prsc0 adon cs3 cs2 cs1 cs0 f adc prsc1 prsc0 4mhz 0 0 2mhz 0 1 1mhz 1 0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000000d1d0 ST7MC1/st7mc2 236/294 10-bit a/d converter (adc) (cont ? d) table 86. adc register map and reset values address (hex.) register label 76543210 2e adccsr reset value eoc 0 prsc1 0 prsc0 0 adon 0 cs3 0 cs2 0 cs1 0 cs0 0 2f adcdrmsb reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 30 adcdrlsb reset value 0 0 0 0 0 0 0 0 0 0 0 0 d1 0 d0 0 ST7MC1/st7mc2 237/294 10 instruction set 10.1 cpu addressing modes the cpu features 17 different addressing modes which can be classified in 7 main groups: the cpu instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 87. cpu addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 ST7MC1/st7mc2 238/294 instruction set overview (cont ? d) 10.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 10.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 10.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 10.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 10.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations ST7MC1/st7mc2 239/294 instruction set overview (cont ? d) 10.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 88. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 10.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative ST7MC1/st7mc2 240/294 instruction set overview (cont ? d) 10.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf ST7MC1/st7mc2 241/294 instruction set overview (cont ? d) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. int pin = 1 (ext. int pin high) jril jump if ext. int pin = 0 (ext. int pin low) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > ST7MC1/st7mc2 242/294 instruction set overview (cont ? d) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z ST7MC1/st7mc2 243/294 11 electrical characteristics 11.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 11.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 11.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5v. they are given only as de- sign guidelines and are not tested. 11.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 11.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 126 . figure 126. pin loading conditions 11.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 127 . figure 127. pin input voltage c l st7 pin v in st7 pin ST7MC1/st7mc2 244/294 11.2 absolute maximum ratings stresses above those listed as ? absolute maxi- mum ratings ? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 11.2.1 voltage characteristics 11.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). for the same reason, unused i/o pins must not be directly tied to v dd or v ss . 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7MC1/st7mc2 246/294 11.3 6operating conditions 11.3.1 general operating conditions figure 128. f cpu max versus v dd note: some temperature ranges are only available with a specific package and memory size. refer to or- dering information. warning : do not connect 12v to v pp before v dd is powered on, as this may damage the device. symbol parameter conditions min max unit f cpu internal clock frequency versus v dd 08mhz v dd extended operating voltage no flash write/erase. analog parameters not guaranteed 3.8 5.5 v standard operating voltage 4.5 5.5 operating voltage for flash write/erase v pp = 11.4 to 12.6v 4.5 5.5 t a ambient temperature range 6 suffix version -40 85 c c suffix version -40 125 f cpu [mhz] supply voltage [v] 8 4 2 1 0 3.5 4.0 4.5 5.5 functionality functionality guaranteed in this area not guaranteed in this area 3.8 6 (unless otherwise specified in the tables of parametric data) ST7MC1/st7mc2 247/294 operating conditions (cont ? d) 11.3.2 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f osc , and t a . notes: 1. data based on characterization results, not tested in production. 11.3.3 auxiliary voltage detector (avd) thresholds subject to general operating condition for v dd , f osc , and t a . notes: 1. data based on characterization results, not tested in production. symbol parameter conditions min typ max unit v it+(lvd) reset release threshold (v dd rise) 4.0 1) 4.2 4.5 v v it-(lvd) reset generation threshold (v dd fall) 3.8 4.0 4.25 v hys(lvd) lvd voltage threshold hysteresis v it+(lvd) -v it-(lvd) 200 mv vt por v dd rise time rate 1) 20 s/v 100 ms/v t g(vdd) width of filtered glitches on v dd 1) (which are not detected by the lvd) 40 ns symbol parameter conditions min typ max unit v it+(avd) 1 ? 0 avdf flag toggle threshold (v dd rise) 4.4 1) 4.7 4.9 1) v v it-(avd) 0 ? 1 avdf flag toggle threshold (v dd fall) 4.2 1) 4.5 4.7 1) v hyst(avd) avd voltage threshold hysteresis ) v it+(avd) -v it-(avd) 200 mv ? v it- voltage drop between avd flag set and lvd reset activated ) v it-(avd) -v it-(lvd) 450 mv ST7MC1/st7mc2 248/294 11.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode for which the clock is stopped). 11.4.1 run and slow modes (flash devices) figure 129. typical i dd in run vs. f cpu figure 130. typical i dd in slow vs. f cpu notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source (section 11.5.3) and the peripheral power consumption. symbol parameter conditions typ max 1) unit i dd supply current in run mode 2) (see figure 129 ) 4.5v v dd 5.5v f osc =16mhz, f cpu =8mhz 12 18 ma supply current in slow mode 2) (see figure 130 ) f osc =16mhz, f cpu =500khz 5 8 ma 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 012345678 fcpu m hz idd (ma) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 012345678 fcpu m hz idd (ma) ST7MC1/st7mc2 249/294 supply current characteristics (cont ? d) 11.4.2 wait and slow wait modes figure 131. typical i dd in wait vs. f cpu figure 132. typical i dd in slow-wait vs. f cpu notes: 1. data based on characterization results, tested in production at v dd max. and f cpu max. 2. measurements are done in the following conditions: - progam executed from ram, cpu running with ram access. the increase in consumption when executing from flash is 50%. - all i/o pins in input mode with a static value at v dd or v ss (no load) - all peripherals in reset state. - lvd disabled. - clock input (osc1) driven by external square wave. - in slow and slow wait mode, f cpu is based on f osc divided by 32. to obtain the total current consumption of the device, add the clock source (section 11.5.3) and the peripheral power consumption. symbol parameter conditions typ max 1) unit i dd supply current in wait mode 2) (see figure 131 ) 4.5v v dd 5.5v f osc =16mhz, f cpu =8mhz 812 ma supply current in slow wait mode 2) (see figure 132 ) fosc=16mhz, fcpu=500khz 3.5 5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 012345678 fcpu mhz idd (ma) 0.0 0.5 1.0 1.5 2.0 2.5 012345678 fcpu mhz idd (ma) ST7MC1/st7mc2 250/294 supply current characteristics (cont ? d) 11.4.3 halt and active-halt modes 1. all i/o pins in push-pull output mode (when applicable) with a static value at v dd or v ss (no load), pll and lvd dis- abled. data based on characterization results, tested in production at v dd max. and f cpu max. 2. all i/o pins in input mode with a static value at v dd or v ss . tested in production at v dd max and f cpu max with clock input osc1 driven by an external square wave; v dd apllied on osc2 to reduce oscillator consumption. consumption may be slightly different with a quartz or resonator. 11.4.4 supply and clock managers the previous current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consump- tion, the two current values must be added (except for halt mode). notes: 1. data based on characterization results, not tested in production. symbol parameter conditions typ max unit i dd supply current in halt mode 1) v dd =5.5v -40 c t a +85 c 0 10 a -40 c t a +125 c50 supply current in active-halt mode 2) 16mhz external clock 1 1.5 ma symbol parameter conditions typ max 1) unit i dd(lvd) lvd supply current halt mode 150 300 a i dd(pll) pll supply current v dd = 5v 700 ST7MC1/st7mc2 251/294 supply current characteristics (cont ? d) 11.4.5 on-chip peripherals n otes: 1. data based on a differential i dd measurement between reset configuration (timer counter running at fcpu/4) and timer counter stopped (only timd bit set). data valid for one timer. 2. data based on a differential i dd measurement betwwen reset configuration (timer stopped ) and timer counter enable (only tce bit set ) 3. data based on a differential i dd measurement between reset configuration (spi disabled) and a permanent spi master communication at maximum speed (data sent equal to 55h). this measurement includes the pad toggling consumption. 4. data based on a differential i dd measurement between sci low power state (scid=1) and a permanent sci data trans- mit sequence. 5. data based on a differnetial i dd measurement between reset configuration (motor control disabled) and the whole mo- tor control cell enable in speed measurement mode. mco outputs are not validated. 6. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. 7. data based on a differential measurement between reset configuration (opamp disabled) and amplification of a sin- ewave (no load, a vcl =1, v dd =5v). symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 1) f cpu =8mhz v dd = 5.0v 50 a i dd(art) art pwm supply current 2) f cpu =8mhz v dd = 5.0v 75 i dd(spi) spi supply current 3) f cpu =8mhz v dd = 5.0v 400 i dd(sci) sci supply current 4) f cpu =8mhz v dd = 5.0v 400 i dd(mtc) mtc supply current 5) f cpu =8mhz v dd = 5.0v 500 i dd(adc) adc supply current when converting 6) f adc =4mhz v dd = 5.0v 400 i dd(opamp) opamp supply current 7) f cpu =8mhz v dd = 5.0v 1500 ST7MC1/st7mc2 252/294 11.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 11.5.1 general timings notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 11.5.2 external clock source figure 133. typical application with an external clock source notes: 1. data based on design simulation and/or technology characteristics, not tested in production. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2312t cpu f cpu =8mhz 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = ? t c(inst) + 10 10 22 t cpu f cpu =8mhz 1.25 2.75 s symbol parameter conditions min typ max unit v osc1h osc1 input pin high level voltage see figure 133 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 1) 25 ns t r(osc1) t f(osc1) osc1 rise or fall time 1) 5 i l oscx input leakage current v ss v in v dd 1 a osc1 osc2 f osc external st7fmc clock source v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) i l 90% 10% v dd ST7MC1/st7mc2 253/294 clock and timing characteristics (cont ? d) 11.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). figure 134. typical application with a crystal or ceramic resonator notes: 1. when pll is used, please refer to the pll characteristics chapter and to the ? supply, reset and clock management ? description chapter (f osc min is 8 mhz with pll). 2. resonator characteristics given by the crystal/ceramic resonator manufacturer. symbol parameter conditions min max unit f osc oscillator frequency 1) 416mhz r f feedback resistor tbd tbd k ? c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) see table below pf i 2 osc2 driving current v dd =5v v in =v ss tbd tbd a oscil. typical crystal or ceramic resonators c l1 [pf] c l2 [pf] reference freq. characteristic 2) ceramic mp murata cstcr4m00g53 4mhz 22 22 ms cstce8m00g53 8mhz 33 33 hs cstce16m0v53 16mhz 33 33 osc2 osc1 f osc c l1 c l2 i 2 r f st7fmc resonator when resonator with integrated capacitors ST7MC1/st7mc2 254/294 clock and timing characteristics (cont ? d) 11.5.4 clock security system with pll table 89. pll characteristics table 90. clock detector characteristics notes: 1. data based on characterization results, not tested in production. symbol parameter min typ max unit fosc pll input frequency range 7 8 mhz output frequency output frequency when the pll attain lock. 16 mhz t lock pll lock time (locked = 1) 50 100 s jitter jitter in the output clock 2 % f cpu cpu clock frequency when vco is con- nected to ground (icd internal clock or back up oscillator ) 3mhz symbol parameter min typ max unit f detect detected minimum input frequency 500 1) khz t setup time needed to detect oscin once ckd is enabled 3 s t hold time needed to detect that oscin stops 3 s ST7MC1/st7mc2 255/294 clock and timing characteristics (cont ? d) table 91. pll and clock detector signal start up sequence notes: 1. lock does not go low without resetting the pllen bit. 2. before setting the cksel bit by software in order to switch to the pll clock, a period of t lock must have elapsed. 3. 2 clock cycles are missing after cksel = 1 4. cksel bit must be set before enabling the css interrupt (cssie=1 ). oscin pllen pll clock lock f clk t lock cssd cssie interrupt t setup t hold 16mhz 6 mhz f vco = oscin clock pll clock 1) cksel 2) 3) (pll and ckd) 4) ST7MC1/st7mc2 256/294 11.6 memory characteristics 11.6.1 ram and hardware registers 11.6.2 flash memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). not tested in production. 2. data based on characterization results, not tested in production. 3. v pp must be applied only during the programming or erasing operation and not permanently for reliability reasons. 4. data based on simulation results, not tested in production 5. in write/erase mode the i dd supply current consumption is the same as in run mode ( section 11.4.1 on page 248 ) symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v dual voltage hdflash memory symbol parameter conditions min 2) typ max 2) unit f cpu operating frequency read mode 0 8 mhz write / erase mode 1 8 v pp programming voltage 3) 4.5v v dd 5.5v 11.4 12.6 v i pp v pp current 4) 5) read (v pp =12v) 200 a write / erase 30 ma t vpp internal v pp stabilization time 10 s t ret data retention t a =55 c 20 years n rw write erase cycles t a =25 c 100 cycles t prog t erase programming or erasing tempera- ture range -40 25 85 c ST7MC1/st7mc2 257/294 11.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 11.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 11.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015) . symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance flash device, v dd = 5v, t a = +25 c, f o- sc = 8mhz, lvd off conforms to iec 1000-4-2 4a flash device, v dd = 5v, t a = +25 c, f o- sc = 8mhz, lvd on conforms to iec 1000-4-2 2b v fftb fast transient voltage burst limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz, pll off conforms to iec 1000-4-4 3b v dd = 5v, t a = +25 c, f osc = 8mhz, pll on conforms to iec 1000-4-4 4a ST7MC1/st7mc2 258/294 emc characteristics (cont ? d) 11.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1 752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. 2. refer to application note an1709 for data on other package types symbol parameter conditions device/ package monitored frequency band max vs. [f osc /f cpu ] unit 8/4mhz 16/8mhz s emi peak level v dd = 5v, t a = +25 c conforming to sae j 1752/3 flash/tqfp64 0.1mhz to 30mhz 8 6 db v 30mhz to 130mhz 8 12 130mhz to 1ghz 1 9 sae emi level 1.5 2.5 - ST7MC1/st7mc2 259/294 emc characteristics (cont ? d) 11.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the application note an1181. 11.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test con- forms to the jesd22-a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 11.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 2500 v v esd(mm) electro-static discharge voltage (machine model) t a = +25 c 250 symbol parameter conditions class 1) lu static latch-up class t a = +25 c t a = +125 c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25 c a ST7MC1/st7mc2 260/294 11.8 i/o port pin characteristics 11.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 3. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7MC1/st7mc2 262/294 i/o port pin characteristics (cont ? d) 11.8.2 output driving current subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 137. typical v ol at v dd =5v (standard) figure 138. typical v ol at v dd =5v (high-sink) figure 139. typical v dd -v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 11.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 11.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 137 ) v dd =5v i io =+5ma 1.2 v i io =+2ma 0.5 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 138 ) i io =+20ma, t a 85 c t a 85 c 1.3 1.5 i io =+8ma 0.6 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 139 ) i io =-5ma, t a 85 c t a 85 c v dd -1.4 v dd -1.6 i io =-2ma v dd -0.7 0246810 iio [ma] 0 0.5 1 1.5 2 2.5 vol [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c 0 5 10 15 20 25 30 iio [ma] 0 0.5 1 1.5 2 vol [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c -8 -6 -4 -2 0 iio [ma] 1 2 3 4 5 6 vdd-voh [v] at vdd=5v ta=-40c ta=25c ta=85c ta=125c ST7MC1/st7mc2 263/294 11.9 control pin characteristics 11.9.1 asynchronous reset pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schmitt trigger switching levels. 3. the i io current sunk must always respect the absolute maximum rating specified in section 11.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 5. the reset network protects the device against parasitic resets. figure 140. typical application with reset pin 1)2)3)4)5) notes: 1. the reset network protects the device against parasitic resets. 2. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). 3. whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 11.9.1 . otherwise the reset will not be taken into account internally. 4. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin (by an external pull-p for example) is less than the absolute maximum value spec- ified for i inj(reset) in section 11.2.2 on page 244 . symbol parameter conditions min typ max unit v il input low level voltage 1) 0.3xv dd v v ih input high level voltage 1) 0.7xv dd v hys schmitt trigger voltage hysteresis 2) 1v v ol output low level voltage 3) v dd =5v i io =+5ma 0.5 1.2 v i io =+2ma 0.2 0.5 i io driving current on reset pin 2 ma r on weak pull-up equivalent resistor 1) v in = v ss, v dd =5v 20 40 80 k ? t w(rstl)out generated reset pulse duration internal reset sources 30 s t h(rstl)in external reset pulse hold time 4) 2.5 s t g(rstl)in filtered glitch duration 5) 450 ns 0.01 f v dd 0.01 f external reset circuit 8) user v dd 4.7k ? st7fmc pulse generator filter r on v dd watchdog lvd reset internal reset required if lvd is disabled recommended if lvd is disabled ST7MC1/st7mc2 264/294 control pin characteristics (cont ? d) 11.9.2 iccsel/v pp pin subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 141. two typical applications with v pp pin 3) notes: 1. data based on design simulation and/or technology characteristics, not tested in production. 2. vpp is also used to program the flash , refer to the flash caracteristics. 3. when the icc mode is not required by the application iccsel/v pp pin must be tied to v ss . symbol parameter conditions min max unit v il input low level voltage 1) v ss 0.2 v v ih input high level voltage 1) 2) icc mode entry v dd -0.1 12.6 i l input leakage current v in =v ss 1 a iccsel/v pp st7mc 10k ? programming tool v pp st7mc ST7MC1/st7mc2 265/294 11.10 timer peripheral characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output...). 11.10.1 8-bit pwm-art auto-reload timer 11.10.2 16-bit timer symbol parameter conditions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 res pwm pwm resolution 8bit v os pwm/dac output step voltage v dd =5v, res=8-bits 20 mv symbol parameter conditions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit ST7MC1/st7mc2 266/294 11.11 communication interface characteristics 11.11.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 142. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss ) ss setup time slave 120 ns t h(ss ) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in ST7MC1/st7mc2 267/294 communication interface characteristics (cont ? d) figure 143. spi slave timing diagram with cpha=1 1) figure 144. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 seenote2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck) ST7MC1/st7mc2 268/294 11.12 motor control characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. 11.12.1 internal reference voltage note : 1. unless otherwise specified, typical data are based on ta=25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. symbol parameter conditions min typ 1) max unit v ref voltage threshold (vr [2:0] = 000) vr [2:0] = 000 v dd *0.04 v example: v dd -v ssa = 5v 0.2 voltage threshold (vr [2:0] = 001) vr [2:0]= 001 v dd *0.12 example: v dd -v ssa = 5v 0.6 voltage threshold (vr [2:0] = 010) vr [2:0] = 010 v dd *0.2 example: v dd -v ssa = 5v 1.0 voltage threshold (vr [2:0] = 011) vr [2:0]= 011 v dd *0.3 example: v dd -v ssa = 5v 1.5 voltage threshold (vr [2:0] = 100) vr [2:0] = 100 v dd *0.4 example: v dd -v ssa = 5v 2.0 voltage threshold (vr [2:0] = 101) vr [2:0]= 101 v dd *0.5 example: v dd -v ssa = 5v 2.5 voltage threshold (vr [2:0] = 110) vr [2:0] = 110 v dd *0.7 example: v dd -v ssa = 5v 3.5 v ref / v ref tolerance on v ref 2.5 10 % ? ST7MC1/st7mc2 269/294 motor control characteristics (cont ? d) 11.12.2 input stage (comparator + sampling) note : 1. the comparator accuracy is dependent of the environment. the offset value is given for a comparison done with all digital i/os stable. negative injection current on the i/os close to the inputs may reduce the accuracy. in particular care must be taken to avoid switching on i/os close to the inputs when the comparator is in use. this phenomenon is even more critical when a big external serial resistor is added on the inputs. 2. this filter is implemented to wait for comparator stabilization and avoid any wrong information during startup. 3. this delay represents the number of clock cycles needed to generate an event as soon as the comparator output or mco outputs change. example : in tachogenerator mode, this means that capture is performed on the 4th clock cycle after comparator com- mutation., i.e. there is a variation of (1/f mtc ) or (1 / f scf ) depending on the case. symbol parameter conditions min typ max unit v in comparator input volt- age range v ssa - 0.1 v dd + 0.1 v v offset comparator offset error 5 40 1) mv i offset input offset current 0 1 a t propag comparator propagation delay 35 100 ns t startup startup filter duration 2) time waited before sampling when com- parator is turned on, i.e. cke=1 or dac=1 (with f periph = 4mhz) 3 s t sampling digital sampling delay 3) time needed to generate a capture in tachogenerator mode as soon as the mci input toggles 4 / f mtc time needed to capture mtim in mzreg (bemf) when sampling during pwm sig- nal off time as soon as mco becomes on 3 / f mtc (see figure 145 ) time needed to set/reset the hst bit when sampling during pwm signal off time as soon as mco becomes on (bemf) 1 / f mtc (see figure 145 ) time needed to generate z event (mtim captured in mzreg) as soon as the com- parator toggles (when sampling at f scf ) 1 / f scf + 3 / f mtc (see figure 146 ) time needed to generate d event (mtim captured in mdreg) as soon as the com- parator toggles 1 / f scf + 3 / f mtc (see figure 146 ) time needed to set/reset the hst bit when sampling during pwm signal on time after a delay (ds>0) as soon as mco becomes on delay programmed in ds bits (mconf) +1 / f mtc (see figure 147 ) time needed to generate z event (mtim in mzreg) when sampling during pwm signal on time after a delay (ds>0) as soon as mco becomes on delay programmed in ds bits (mconf) + 3 / f mtc (see figure 147 ) time needed to generate z event (mtim captured in mzreg) when sampling dur- ing pwm signal on time at f scf after a delay (ds>0) delay programmed in ds bits (mconf) + 1 / f scf + 3 / f mtc (see figure 147 ) ST7MC1/st7mc2 270/294 motor control characteristics (cont ? d) figure 145. example 1: waveforms for zero-crossing detection with sampling at the end of pwm off-time figure 146. example 2: waveforms for zero-crossing detection with sampling at f scf f mtc mcox comparator output hst (mcrc) mtim mzreg a5 a6 a7 xx a5 sampling time sample f mtc f scf comparator output hst (mcrc) mtim mzreg a5 a6 a7 xx a6 sampling time sample ST7MC1/st7mc2 271/294 motor control characteristics (cont ? d) figure 147. example 3: waveforms for zero-crossing detection with sampling after a delay during pwm on-time figure 148. example 4: waveforms for zero-crossing detection with sampling after a delay at f scf f mtc mcox comparator output hst (mcrc) mtim mzreg a5 a6 a7 xx a6 sampling time sample delay from ds bits f mtc f scf comparator output hst (mcrc) mtim mzreg a5 a6 a7 xx a7 sampling time sample mcox delay from ds bits ST7MC1/st7mc2 272/294 motor control characteristics (cont ? d) 11.12.3 input stage (current feedback comparator + sampling) note : 1. the comparator accuracy is dependent of the environment. the offset value is given for a comparison done with all digital i/os stable. negative injection current on the i/os close to the inputs may reduce the accuracy. in particular care must be taken to avoid switching on i/os close to the inputs when the comparator is in use. this phenomenon is even more critical when a big external serial resistor is added on the inputs. 2. this filter is implemented to wait for comparator stabilization and avoid any wrong information during startup. 3.this delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput chang- es. example : when cff=0 (detection is based on a single detection), mco outputs are turned off at the 4th clock cycle after comparator commutation, i.e. there is a variation of (1/f mtc ) or (4 / f periph ) depending on the case. symbol parameter conditions min typ max unit v in comparator input voltage range v ssa - 0.1 v dd + 0.1 v v offset comparator offset error 5 40 1) mv i offset input offset current 0 1 a t propag comparator propagation delay 1) 35 100 ns t startup startup filter duration 2) time waited before sampling when comparator is turned on, i.e. cke=1 or dac=1 (with f periph = 4mhz) 3 s t sampling digital sampling delay 3) time needed to turn off the mcos when comparator out- put rises (cff=0) 4 / f mtc (see figure 149 ) time between a comparator toggle (current loop event) and bit cl becoming set (cff=0) 2 / f mtc (see figure 149 ) time needed to turn off the mcos when comparator out- put rises (cff=x) (1+x) * (4 / f periph ) + (3 / f mtc ) (see figure 150 ) time between a comparator toggle (current loop event) and bit cl becoming set (cff=x) (1+x) * (4 / f periph ) + (1 / f mtc ) (see figure 150 ) ST7MC1/st7mc2 273/294 motor control characteristics (cont ? d) figure 149. example 1 : waveforms for overcurrent detection with current feedback filter off figure 150. example 2 : waveforms for overcurrent detection with current feedback filter on (cff=001 => 2 consecutive samples are needed to validate the overcurrent event) f mtc mcox comparator output cl (mcrc) sampling time sample f mtc f periph /4 comparator output cl (mcrc) sampling time sample mcox ST7MC1/st7mc2 274/294 11.13 operational amplifier characteristics subject to general operating conditions for f osc , and t a unless otherwise specified. (t a = -40..+125 o c, v dd -v ssa = 4.5..5.5v unless otherwise specified note : 1. a vcl = closed loop gain 2. data based on characterization results, not tested in production. 3. after offset compensation has been performed. 4. the amplifier accuracy is dependent of the environment. the offset value is given for a measurement done with all digital i/os stable. negative injection current on the i/os close to the inputs may reduce the accuracy. in particular care must be taken to avoid switching on i/os close to the inputs when the opamp is in use. this phenomenon is even more critical when a big external serial resistor is added on the inputs. 5. the data provided from simulations (not tested in production) to guide the user when re-calibration is needed. 6. the data provided from simulations (not tested in production). symbol parameter conditions min typ max unit r l resistive load (max 500ua @ 5v) 10 k ? c l capacitive load at v out pin 150 pf v cmir common mode input range v ssa v dd /2 v v io input offset voltage ( + or - ) 3) after calibration, v ic =1v 2.5 10 4) mv ? v io input offset voltage drift from the calibrated voltage, temperature conditions with respect to tempera- ture 8.5 5) v/ o c with respect to common mode input 1 5) mv/v with respect to supply 3.1 5) mv/v cmr common mode rejection ratio highgain=0 @ 100khz 74 db svr supply voltage rejection ratio @ 100khz 50 2) 65 db a vd voltage gain r l =10k ? (1.5) 2) 12 v/mv v sat_oh high level ouptut saturation volt- age (v dd -v out ) r l =10k ? 60 90 2) mv v sat_ol low level output saturation volt- age r l =10k ? 30 90 2) mv gbp gain bandwidth product highgain=0 2 2) 46 2) mhz highgain=1 7 2) 11 15 2) sr + slew rate while rising highgain=0 (a vcl =1, r l =10k ? , c l =150pf, v i =1.75v to 2.75v) 1) 1 2) 2v/ s sr - slew rate while falling highgain=0 (a vcl =1, r l =10k ? , c l =150pf, v i =1.75v to 2.75v) 1) 2.5 2) 7.5 v/ s m phase margin highgain=0 73 degrees highgain=1 75 t wakeup wakeup time for the opamp from off state 0.8 6) 1.6 6) s ST7MC1/st7mc2 275/294 11.14 10-bit adc characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. figure 151. r ain max. vs f adc with c ain =0pf 3) symbol parameter conditions min typ max unit v aref analog reference voltage 3 v dd v f adc adc clock frequency 4 mhz v ain conversion voltage range 1) v ssa v aref v i lkg positive input leakage current for analog input -40 c t a 85 c range 250 na other t a ranges 1 a negative input leakage current on analog pins v in < v ss, | i in |< 400a on adjacent analog pin 56 a r ain external input impedance see figure 151 and figure 152 2)3)4) k ? c ain external capacitor on analog input pf f ain variation freq. of analog input signal hz c adc internal sample and hold capacitor 6 pf t adc conversion time (sample+hold) f cpu =8mhz, f adc =4mhz, adsts bit in mccbcr register = 0 3.5 s - sample capacitor loading time - hold conversion time 4 10 1/f adc conversion time (sample+hold) f cpu =8mhz, f adc =4mhz, adsts bit in mccbcr register = 1 6.5 s - sample capacitor loading time - hold conversion time 16 10 1/f adc r aref analog reference input resistor 11 k ? 0 5 10 15 20 25 30 35 40 45 0103070 c parasitic (pf) max. r ain (kohm) 2 mhz 1 mhz ST7MC1/st7mc2 276/294 figure 152. recommended c ain & r ain values. 4) figure 153. typical application with adc notes: 1. when v ssa pins are not available on the pinout, the adc refer to v ss . 2. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k ? ). data based on characterization results, not tested in production. 3. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad ca- pacitance (3pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. 4. this graph shows that depending on the input signal variation (f ain ), c ain can be increased for stabilization time and decreased to allow the use of a larger serial resistor (r ain) . 0.1 1 10 100 1000 0.01 0.1 1 10 f ain (khz) max. r ain (kohm) cain 10 nf cain 22 nf cain 47 nf ainx st7mc v dd i l 1 a v t 0.6v v t 0.6v v ain r ain v aref v ssa 0.1 f v dd r aref c adc 6pf c ain 10-bit a/d conversion 2k ?( max ) ST7MC1/st7mc2 277/294 11.14.1 analog power supply and reference pins depending on the mcu pin count, the package may feature separate v aref and v ssa analog power supply pins. these pins supply power to the a/d converter cell and function as the high and low reference voltages for the conversion. in some packages, v aref and v ssa pins are not available (refer to section 2 on page 5 ). in this case the an- alog supply and reference pads are internally bonded to the v dd and v ss pins. separation of the digital and analog power pins al- low board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see section 11.14.2 general pcb design guidelines ). 11.14.2 general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. ? use separate digital and analog planes. the an- alog ground plane should be connected to the digital ground plane via a single point on the pcb. ? filter power to the analog power planes. it is rec- ommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the st7 power supply pins and a 1 to 10f ca- pacitor close to the power source (see figure 154 ). ? the analog and digital power supplies should be connected in a star nework. do not use a resis- tor, as v aref is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. ? properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital out- puts on the same i/o port as the a/d input being converted. figure 154. power supply filtering v ss v dd 0.1 f 10pf v dd st7mc v aref v ssa power supply source st7 digital noise filtering external noise filtering 1 to 10 f 0.1 f 10pf (if needed) (if needed) ST7MC1/st7mc2 278/294 10-bit adc characteristics (cont ? d) adc accuracy with v dd =5.0v notes: 1. adc accuracy vs. negative injection current: injecting negative current may reduce the accuracy of the conversion being performed on another analog input. the effect of negative injection current on analog pins is specified in section 11.14 . any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 11.8 does not affect the adc accuracy. 2. data based on characterization results, monitored in production. figure 155. adc accuracy characteristics notes: 1. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 4 lsb for each 10k ? increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 2. data based on characterization results with t a =25 c. 3. data based on characterization results over the whole temperature range, monitored in production. symbol parameter conditions typ max unit |e t | total unadjusted error 1) v aref =3.0v to 5.0v, f cpu =8mhz, f adc =4mhz, r ain <10k ? 4 lsb |e o | offset error 1) 2.5 4 2) |e g | gain error 1) 24 2) |e d | differential linearity error 1) 24.5 2) |e l | integral linearity error 1) 24.5 2) e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v aref v ssa ST7MC1/st7mc2 279/294 12 package characteristics 12.1 package mechanical data figure 156. 80-pin 14x14 thin quad flat package figure 157. 64-pin 14x14 thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.65 0.026 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 80 a a2 a1 b e h c l l1 e e1 d1 d dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.80 0.031 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 c h l l1 e b a a1 a2 e e1 d d1 ST7MC1/st7mc2 280/294 package characteristics (cont ? d) figure 158. 44-pin thin quad flat package figure 159. 32-pin thin quad flat package 5package characteristics (cont ? d) 6 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.000 0.008 d 12.00 0.472 d1 10.00 0.394 e 12.00 0.472 e1 10.00 0.394 e 0.80 0.031 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 a a2 a1 b e l1 l h c e e1 d d1 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 e 9.00 0.354 e1 7.00 0.276 e 0.80 0.031 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 32 h c l l1 b e a1 a2 a e e1 d d1 ST7MC1/st7mc2 281/294 package characteristics (cont ? d) figure 160. 32-pin plastic dual in-line package, shrink 400-mil width figure 161. 56-pin plastic dual in-line package, shrink 600-mil width dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 ec 1.40 0.055 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n 32 d b2 b e a a1 a2 l e1 e ec c ea eb dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n 56 e 0.015 gage plane eb eb ea e1 e c a a2 a1 e b b2 d e b ST7MC1/st7mc2 282/294 package characteristics (cont ? d) 12.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) tqfp80 14x14 tqfp64 14x14 tqfp44 10x10 tqfp32 7x7 sdip32 400mil sdip56 600mil 55 55 68 80 63 45 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c ST7MC1/st7mc2 283/294 12.3 soldering and glueability information recommended soldering information given only as design guidelines. figure 162. recommended wave soldering profile (with 37% sn and 63% pb) figure 163. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages dedicated to molding compound with silicone: heraeus: pd945, pd955 loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [ c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80 c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [ c] ramp up 2 c/sec for 50sec 90 sec at 125 c 150 sec above 183 c ramp down natural 2 c/sec max tmax=220+/-5 c for 25 sec ST7MC1/st7mc2 284/294 13 st7mc device configuration and ordering information each device is available for production in rom versions and in user programmable versions (flash) as well as in factory coded versions (fastrom). st7mc are rom devices. st7pmc devices are factory advanced service technique rom (fastrom) versions: they are programmed flash devices. st7fmc flash devices are shipped to custom- ers with a default content (ffh), while rom/fas- trom factory coded parts contain the code sup- plied by the customer. this implies that flash de- vices have to be configured by the customer using the option bytes while the rom devices are facto- ry-configured. 13.1 flash option bytes the option bytes allow the hardware configuration of the microcontroller to be selected. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default con- tent of the flash is fixed to ffh. this means that all the options have ? 1 ? as their default value. option byte 0 opt7= wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode opt6= wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) opt5 = cksel clock source selection. 0: pll clock selected 1: oscillator clock selected opt4:3= vd[1:0] voltage detection these option bits enable the voltage detection block (lvd, and avd). opt2 = rstc reset clock cycle selection this option bit selects the number of cpu cycles applied during the reset phase and when exiting halt mode. for resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 cpu cycles 1: reset phase with 256 cpu cycles note: when the pll clock is selected (cksel=0), the reset clock cycle selection is forced to 4096 cpu cycles. opt1= div2 divider by 2 1: div2 divider disabled 0: div2 divider enabled (in order to have 8 mhz re- quired for the pll) opt0= fmp_r flash memory read-out protection this option indicates if the user flash memory is protected against read-out. this protection is based on a read and write protection of the mem- ory in test modes and icp mode. erasing the op- tion bytes when the fmp_r option is selected causes the whole user memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.3.1 on page 20 for more details. 0: read-out protection enabled 1: read-out protection disabled static option byte 0 70 static option byte 1 70 wdg cksel vd rstc div2 fmp_r pkg mco halt sw 10 21 0 default value 111111111 1 11 1 1 1 1 selected low voltage detector vd1 vd0 lvd and avd on 0 0 lvd on and avd off 0 1 lvd and avd off 10 11 selected low voltage detector vd1 vd0 ST7MC1/st7mc2 285/294 st7mc device configuration and ordering information (cont ? d) option byte 1 opt7:5= pkg[2:0] package selection these option bits are used to select the device package. opt4:2= reserved opt1:0 = mco motor control output options mco port under reset. selected package pkg2 pkg1 pkg0 tqfp32 / sdip32 0 0 0 tqfp44 0 0 1 sdip 56 0 1 0 tqfp64 0 1 1 tqfp80 1 x x motor control output bit 1 bit 0 hiz 0 0 low 0 1 high 1 0 hiz 1 1 ST7MC1/st7mc2 286/294 13.2 device ordering information and transfer of customer code the fastrom or rom contents are to be sent on diskette, or by electronic means, with the hexadec- imal file in .s19 format generated by the develop- ment tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 92. supported part numbers note: /xxx stands for the rom or fastrom code assigned by stmicrolectronics. part number program memory (bytes) ram (bytes) temp. range package st7fmc1k2t6 8k flash 384 -40 c +85 ctqfp32 st7fmc1k2tc -40 c +125 ctqfp32 st7fmc1k2b6 -40 c +85 csdip32 st7fmc2s4t6 16k flash 768 -40 c +85 ctqfp44 st7fmc2s4tc -40 c +125 ctqfp44 st7fmc2s5t6 24k flash 1024 -40 c +85 ctqfp44 st7fmc2s5tc -40 c +125 ctqfp44 st7fmc2n6b6 32k flash 1024 -40 c +85 csdip56 st7fmc2r6t6 -40 c +85 ctqfp64 st7fmc2r7t6 48k flash 1536 -40 c +85 ctqfp64 st7fmc2m9t6 60k flash 1536 -40 c +85 ctqfp80 ST7MC1k2t6/xxx 8k rom 384 -40 c +85 c tqfp32 ST7MC1k2tc/xxx -40 c +125 c tqfp32 ST7MC1k2b6/xxx -40 c +85 c sdip32 st7mc2s4t6/xxx 16k rom 768 -40 c +85 c tqfp44 st7mc2s4tc/xxx -40 c +125 c tqfp44 st7mc2s5t6/xxx 24k rom 1024 -40 c +85 c tqfp44 st7mc2s5tc/xxx -40 c +125 c tqfp44 st7mc2n6b6/xxx 32k rom 1024 -40 c +85 c sdip56 st7mc2r6t6/xxx -40 c +85 c tqfp64 st7mc2r7t6/xxx 48k rom 1536 -40 c +85 c tqfp64 st7mc2m9t6/xxx 60k rom 1536 -40 c +85 c tqfp80 st7pmc1k2t6/xxx 8k fastrom 384 -40 c +85 c tqfp32 st7pmc1k2tc/xxx -40 c +125 c tqfp32 st7pmc1k2b6/xxx -40 c +85 c sdip32 st7pmc2s4t6/xxx 16k fastrom 768 -40 c +85 c tqfp44 st7pmc2s4tc/xxx -40 c +125 c tqfp44 st7pmc2s5t6/xxx 24k fastrom 1024 -40 c +85 c tqfp44 st7pmc2s5tc/xxx -40 c +125 c tqfp44 st7pmc2n6b6/xxx 32k fastrom 1024 -40 c +85 c sdip56 st7pmc2r6t6/xxx -40 c +85 c tqfp64 st7pmc2r7t6/xxx 48k fastrom 1536 -40 c +85 c tqfp64 st7pmc2m9t6/xxx 60k rom 1536 -40 c +85 c tqfp80 contact st sales office for product availability ST7MC1/st7mc2 287/294 st7mc device configuration and ordering information (cont ? d) st7mc microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom or fastrom code* : . . . . . . . . . . . . *the rom or fastrom code name is assigned by stmicroelectronics. rom or fastrom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max) authorized characters are letters, digits, '.', '-', '/' and spaces only. temperature range: [ ] - 40 c to + 85 c[ ] - 40 c to + 125 c div2 [ ] disabled [ ] enabled cksel [ ] oscillator clock [ ] pll clock watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset readout protection: [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled avd interrupt (if lvd enabled) [ ] disabled [ ] enabled reset delay [ ] 256 cycles [ ] 4096 cycles supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --------------- rom --------------- | | -------------------- 8k -------------------- | | -------------------- 16k -------------------- | | -------------------- 24k -------------------- | | -------------------- 32k -------------------- | | -------------------- 48k -------------------- | | -------------------- 60k -------------------- tqfp32: | [ ] ST7MC1k2 | | | | | sdip32: [ ] ST7MC1k2 tqfp44: | | [ ] st7mc2s4 | [ ] st7mc2s5 | | | sdip56: | | | | [ ] st7mc2n6 | | tqfp64: | | | | [ ] st7mc2r6 | [ ] st7mc2r7 | tqfp80 | | | | | | [ ] st7mc2m9 --------------- fastrom --------------- | | -------------------- 8k -------------------- | | -------------------- 16k -------------------- | | -------------------- 24k -------------------- | | -------------------- 32k -------------------- | | -------------------- 48k -------------------- | | -------------------- 60k -------------------- tqfp32: | [ ] st7pmc1k2| | | | | sdip32: [ ] st7pmc1k2 tqfp44: | | [ ] st7pmc2s4| [ ] st7pmc2s5 | | | sdip56: | | | | [ ] st7pmc2n6 | | tqfp64: | | | | [ ] st7pmc2r6 | [ ] st7pmc2r7| tqfp80 | | | | | | [ ] st7pmc2m9 [ ] tape & reel [ ] tray (tqfp package only) [ ] tube (sdip package only) ST7MC1/st7mc2 288/294 st7mc device configuration and ordering information (cont ? d) 13.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//www.st.com tools from these manufacturers include c compli- ers, emulators and gang programmers. three types of development tool are offered by st, all of them connect to a pc via a parallel (lpt) port or a usb port: see table 93 and table 94 for more details. table 93. stmicroelectronics tool features table 94. dedicated stmicroelectronics development tools note : 1. flash programming interface for flash devices. in-circuit emulation programming capability 1) software included st7 emu3 emulator yes, powerful emulation features including trace/ logic analyzer yes with icc add-on st7 cd rom with: ? st7 assembly toolchain ? stvd7 powerful source level debugger for winxp, win 9x, win 2000, me and nt4.0 ? c compiler demo versions windows programming tools for winxp, win 9x , win 2000, me and nt4.0 st7 programming board no yes (all packages) supported products st7 emu3 emulator ST7MC1, st7mc2 st7mdt50-emu3 ST7MC1/st7mc2 289/294 st7mc device configuration and ordering information (cont ? d) 13.3.1 package/socket footprint proposal table 95. suggested list of socket types package / probe socket reference emulator adapter tqfp64 14x14 cab 3303262 cab 3303351 tqfp80 14x14 yamaichi ic149-080-*51-*5 yamaichi icp-080-7 tqfp32 7x7 ironwood sf-qfe32sa-l-01 ironwood sk-uga06/32a-01 tqfp44 10x10 yamaichi ic149-044-*52-*5 yamaichi icp-044-5 sdip32 standard standard sdip56 standard standard ST7MC1/st7mc2 290/294 13.4 st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i 2 c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso ? d) an1042 st7 routine for i 2 c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i 2 c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16 bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note ST7MC1/st7mc2 291/294 an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 product optimization an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite programming and tools an 978 st7 visual debug software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1477 emulated data eeprom with xflash memory an1478 porting an st7 panta project to codewarrior ide identification description ST7MC1/st7mc2 292/294 an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port system optimization an1827 implementation of sigma-delta adc with st7flite05/09 identification description ST7MC1/st7mc2 293/294 14 summary of changes revision main changes date 2.0 added iccsel to v pp pin ( section 2 on page 5 ) changed port configuration column in table 1 on page 11 changed scibrr reset value (00h) in table 2, ? hardware register map, ? on page 16 added one sentence in ? main features ? section in page 23 removed references to div2 bit in the sicsr register ( page 31 ) added div128 in figure 17 on page 32 removed cautions on trap and mces interrupts on page 36 changed pwm art row in table 8, ? interrupt mapping, ? on page 40 changed section 8.5.1 and table 12, ? port configuration, ? on page 54 added caution to ? external clock and event detector mode ? section. changed section 9.6 motor controller (mtc) changed table 86, ? adc register map and reset values, ? on page 236 changed note 2 in section 11.2 absolute maximum ratings on page 244 changed section 11.3.1 on page 246 changed section 11.5.4 on page 254 changed section 11.9.2 on page 264 added section 11.12 on page 268 added section 11.13 on page 274 changed section 13 on page 284 (introduction) changed option byte 1 in section 13.1 on page 284 added reference to an1635 in section 13.2 on page 286 nov 03 2.1 added sdip32 package option: symbol & device summary updated on page 1 package pinout diagram added figure 4. "32-pin sdip package pinouts" page 7 updated table 1. "st7mc device pin description" page 11 changed 9.6.8.5 "current feedback amplifier" page 184 to include sdip32 changed 12.2 "thermal characteristics" page 282 to include sdip32 added sdip32 to table 92. "supported part numbers" page 286 added sdip32 to table 95. "suggested list of socket types" page 289 added figure 160. "32-pin plastic dual in-line package, shrink 400-mil width" page 281 altered figure 4. "32-pin sdip package pinouts" page 7 such that ei0 does not include pd0 modifications made to text on page 1 under ? motor control peripheral ? subheading alteration of 11.3.1 "general operating conditions" page 246 data plus addition of corre- sponding figure 128. "fcpu max versus v dd " page 246 added consumption graphs and values or run, wait, slow, slow-wait modes added values into 11.3.3 "auxiliary voltage detector (avd) thresholds" page 247 altered values of 11.4.4 "supply and clock managers" page 250 added values into 11.4.5 "on-chip peripherals" page 251 added values into 11.5.3 "crystal and ceramic resonator oscillators" page 253 added values into 11.6.2 "flash memory" page 256 updated esd (machine model) value in section 11.7.3.1 on page 259 added values into 11.7.3.2 "static and dynamic latch-up" page 259 altered values and table in 11.13operational amplifier characteristics put note referring to pc4 in all pinouts and in table 1 on page 11 moved section ? 10-bit a/d converter (adc) ? from 9.6.14 to section 9.8 figure 76 on page 144 , mcrb changed to mcrc, freq(t=1s) replaced by f scf table in section 11.5.3 on page 253 updated with reference to capacitance table updated emulator tool features, table 93 device alteration: st7mc2 24k has 1024bytes ram instead of 768bytes: updated device summary table page 1, table 92. on page 286 negative injection note addition added to section 11.12.2 , section 11.12.3 and section 11.13 ? even / odd ? reworded as ? high / low ? from section 9.6.2 to section 9.6.13 inclusive. sr=1 column added to table 27 on page 146 and table 71 on page 212 thermal characteristics section 12.2 values updated apr 04 ST7MC1/st7mc2 294/294 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com |
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